Datasheet

TX_CLK
TX_EN
PMD Output Pair
0 0
1 1
PMD Output Pair
t
1
t
2
TX_CLK
TX_EN
TXD
PMD Output Pair
t
1
TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
9.6.13 10Base-T Transmit Timing (Start of Packet)
Table 9-13. 10Base-T Transmit Timing (Start of Packet)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
t
1
Transmit Output Delay from the Falling Edge of TX_CLK 10Mbs MII mode 5.8 bits
(1) (1) 1 bit time = 100ns in 10Mb/s.
Figure 9-13. 10Base-T Transmit Timing (Start of Packet)
9.6.14 10Base-T Transmit Timing (End of Packet)
Table 9-14. 10Base-T Transmit Timing (End of Packet)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
End of Packet High Time (with ‘0’ ending bit) 250 310 ns
t
2
End of Packet High Time (with ‘1’ ending bit) 250 310 ns
Figure 9-14. 10Base-T Transmit Timing (End of Packet)
84 Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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