Datasheet

DATA
(T/R)
IDLE
PMDInputPair
CRS
T0347-01
t
1
IDLE
(J/K)
Data
t
1
CRS
PMDInputPair
RXD[3:0]
RX_DV
RX_ER
T0346-01
t
2
TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
9.6.9 100Base-TX Receive Packet Latency Timing
Table 9-9. 100Base-TX Receive Packet Latency Timing
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
(2)
t
1
Carrier Sense ON Delay
(3)
100Mbs Normal mode 14 bits
t
2
Receive Data Latency 100Mbs Normal mode 19 bits
100Mb normal mode with fast RXDV
t
2
Receive data latency
(4)
15 bits
detection ON
(1) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
(2) 1 bit time = 10 ns in 100Mbs mode
(3) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(4) Fast RXDV detection could be enabled by setting bit[1] of CR1 (address 0x0009).
Figure 9-9. 100Base-TX Receive Packet Latency Timing
9.6.10 100Base-TX Receive Packet Deassertion Timing
Table 9-10. 100Base-TX Receive Packet Deassertion Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Carrier Sense OFF Delay
(1)
100Mbs Normal mode 19 bits
(2)
(1) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100Mbs mode
Figure 9-10. 100Base-TX Receive Packet Deassertion Timing
82 Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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