Datasheet

TX_CLK
TXD
TX_EN
PMD Output Pair
(T/R)DATA IDLE
(T/R)
DATA
IDLE
T0344-01
t
1
TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
9.6.7 100Base-TX Transmit Packet Deassertion Timing
Table 9-7. 100Base-TX Transmit Packet Deassertion Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_CLK to PMD Output Pair deassertion 100Mbs Normal mode 4.6 bits
Figure 9-7. 100Base-TX Transmit Packet Deassertion Timing
80 Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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