Datasheet

TX_CLK
TX_EN
TXD
PMD Output Pair
(J/K)
IDLE
DATA
T0343-01
t
1
RX_CLK
Valid Data
RXD[3:0]
RX_DV
RX_ER
T0342-01
t
1
t
2
t
3
TLK105
TLK106
www.ti.com SLLSEB8A –AUGUST 2012–REVISED MARCH 2013
9.6.5 100Mb/s MII Receive Timing
Table 9-5. 100Mb/s MII Receive Timing
PARAMETER
(1)
TEST CONDITIONS MIN TYP MAX UNIT
t
1
RX_CLK High Time
100Mbs Normal mode 16 20 24 ns
t
2
RX_CLK Low Time
t
3
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100Mbs Normal mode 10 30 ns
(1) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
Figure 9-5. 100Mb/s MII Receive Timing
9.6.6 100Base-TX Transmit Packet Latency Timing
Table 9-6. 100Base-TX Transmit Packet Latency Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_CLK to PMD Output Pair Latency 100Mbs Normal mode
(1)
4.8 bits
(2)
(1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the 'J' code group as output from the PMD Output Pair. 1 bit time = 10ns in 100Mbs mode.
(2) 1 bit time is equal 10 nS in 100 Mb/s mode.
Figure 9-6. 100Base-TX Transmit Packet Latency Timing
Copyright © 2012–2013, Texas Instruments Incorporated Electrical Specifications 79
Submit Documentation Feedback
Product Folder Links: TLK105 TLK106