Datasheet

TX_CLK
TXD[3:0]
TX_EN
Valid Data
T0341-01
t
1
t
2
t
4
t
3
MDC
MDC
MDIO (Output)
MDIO (Input)
Valid Data
T0340-01
t
1
t
2
t
4
t
3
TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
9.6.3 MII Serial Management Timing
Table 9-3. MII Serial Management Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
MDC Frequency 2.5 25 MHz
t
2
MDC to MDIO (Output) Delay Time 0 30 ns
t
3
MDIO (Input) to MDC Hold Time 10 ns
t
4
MDIO (Input) to MDC Setup Time 10 ns
Figure 9-3. MII Serial Management Timing
9.6.4 100Mb/s MII Transmit Timing
Table 9-4. 100Mb/s MII Transmit Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_CLK High Time
100Mbs Normal mode 16 20 24 ns
t
2
TX_CLK Low Time
t
3
TXD[3:0], TX_EN Data Setup to TX_CLK 100Mbs Normal mode 10 ns
t
4
TXD[3:0], TX_EN Data Hold from TX_CLK 100Mbs Normal mode 0 ns
Figure 9-4. 100Mb/s MII Transmit Timing
78 Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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