Datasheet

V
CC
XI Clock
Hardware
RESET
T0339-01
t
1
VDD
Hardware RESET
Dual function pins
Become enabled
As outputs
t 1
TLK105
TLK106
www.ti.com SLLSEB8A –AUGUST 2012–REVISED MARCH 2013
9.6 AC Specifications
9.6.1 Power Up Timing
Table 9-1. Power Up Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Time from powerup to hardware-configuration pin
t
1
transition to output-driver function, using internal 100 270 ms
POR (RESET pin tied high)
Figure 9-1. Power Up Timing
NOTE
It is important to choose pullup and-or pulldown resistors for each of the hardware
configuration pins that provide fast RC time constants in order to latch in the proper value
prior to the pin transitioning to an output driver.
9.6.2 Reset Timing
Table 9-2. Reset Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
XI Clock must be stable for minimum of 1ms
t
1
RESET pulse width 1 µs
during RESET pulse low time.
Figure 9-2. Reset Timing
Copyright © 2012–2013, Texas Instruments Incorporated Electrical Specifications 77
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