Datasheet

TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042 (continued)
BIT NAME DEFAULT FUNCTION
3:0 Phase Shift <0000>,RW TX Clock Phase Shift Value:
Value The value of this register represents the current phase shift between Reference clock at XI and MII
Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4
times the difference (in nSec).
For example, if the value of this register is 0x2, Writing 0x9 to this register shifts TX_CLK by 28nS (4
times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of
10) in case of writing value bigger than 10, the updated value is the written value modulo 10.
8.19 Voltage Regulator Control Register (VRCR)
This register gives the host processor the ability to power down the voltage-regulator block of the PHY via
register access. This power-down operation is available in systems operating with an external power
supply.
Table 8-34. Voltage Regulator Control Register (VRCR), address 0x00D0
BIT NAME DEFAULT FUNCTION
15 VRPD 0, RW, SC Voltage Regulator Power Down:
1 = Power Down. Allow the system to power down the voltage regulator block of the PHY
using register access.
0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT
pin.
14:4 RESERVED <000 0000 0000>, RESERVED: Must be written as 0.
RW
3:0 VR Control <0000>, RW Voltage Regulator Control This value should be ignored on read. To write to this register,
perform a read followed by a write with the desired value.
8.20 Cable Diagnostic Configuration/Result Registers (TLK106)
8.20.1 ALCD Control and Results 1 (ALCDRR1)
Table 8-35. ALCD Control and Results 1 (ALCDRR1), address 0x0155
BIT BIT NAME DEFAULT DESCRIPTION
15 alcd_start <0>, SC 1 = Start ALCD
14:13 <00>, RO RESERVED: Writes ignored, read as 0.
12 alcd_done <0>, RO TPTD Diagnostic Bypass
1 = Bypass TPTD diagnostic. TDR on TPTD pair is not executed.
0 = TDR is executed on TPTD pair
11:4 alcd_out1 <0000 alcd_out1
0000>, RO
3 RESERVED <0>, RO RESERVED: Writes ignored, read as 0
2:0 alcd_ctrl <001>,RW Control of ALCD Average factor
8.20.2 Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
Use CDSCR1 to select the channel for the cable diagnostics test. CDSCR1 contains the enable and
bypass bits for the diagnostic tests, and defines the number of executed and averaged TDR sequences.
CDSCR2 - CDSCR4 configure other parameters for cable diagnostics.
Table 8-36. Cable Diagnostic Specific Control Register (CDSCR), address 0x0170
BIT BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0,RO RESERVED: Writes ignored, read as 0.
68 Register Block Copyright © 2012–2013, Texas Instruments Incorporated
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