Datasheet

TLK105

TLK106

SLLSEB8A –AUGUST 2012–REVISED MARCH 2013

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Table 8-16. Register Control Register (REGCR), address 0x000D

BIT BIT NAME DEFAULT DESCRIPTION

15:14 Function 0, RW 00 = Address

01 = Data, no post increment

10 = Data, post increment on read and write

11 = Data, post increment on write only

13:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

4:0 DEVAD 0, RW Device Address: In general, these bits [4:0] are the device address DEVAD that directs any

accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the TLK10x uses the

vendor specific DEVAD [4:0] = “11111” for accesses. All accesses through registers REGCR and

ADDAR should use this DEVAD. Transactions with other DEVAD are ignored.

8.2.2 Address or Data Register (ADDAR)

This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register

(0x000D) to provide the access by indirect read/write mechanism to the extended register set.

Table 8-17. Data Register (ADDAR), address 0x000E

BIT BIT NAME DEFAULT DESCRIPTION

15:0 Addr/data 0, RW If REGCR register 15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the

MMD DEVAD's data register

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