Datasheet

TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
Table 8-4. Basic Mode Control Register (BMCR), address 0x0000 (continued)
BIT BIT NAME DEFAULT DESCRIPTION
0 = Normal operation
Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit
is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is
initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected
by the management entity clearing this bit.
8 Duplex Mode 1, Pin_Strap Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be
selected.
1 = Full Duplex operation
led control 0 = Half Duplex operation
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled
0 = Normal operation
When set, this bit causes the COL signal to be asserted in response to the assertion of
TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to
the de-assertion of TX_EN.
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.
44 Register Block Copyright © 2012–2013, Texas Instruments Incorporated
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