Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History

TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
2.8 10 Mb/s and 100 Mb/s PMD Interface
PIN
TYPE DESCRIPTION
NAME NO.
Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically
configured to either 10BASE-T or 100BASE-TX signaling.
TD–, TD+ 8, 9 I/O
In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 1.8V
or 3.3V bias for operation.
Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept
either 100BASE-TX or 10BASE-T signaling.
RD–, RD+ 5, 6 I/O
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require
1.8V or 3.3V bias for operation.
2.9 Power and Bias Connections
PIN
TYPE DESCRIPTION
NAME NO.
RBIAS 3 I Bias Resistor Connection. Use a 4.99kΩ 1% resistor connected from RBIAS to GND.
1.8V Power Feedback Output. A 1μF capacitor (ceramic preferred), should be placed close to the
V18_PFBOUT 40 O
V18_PFBOUT.
In single supply operation, connect this pin should be connected to V18_PFBIN1 and V18_PFBIN2 (pin
2 and pin 4). See Figure 2-1 for proper placement pin.
In multiple supply operation, when supplying 1.8V from external supply, this pin should be connected
together with VDD33_V18 (pin 41), V18_PFBIN1 and V18_PFBIN2 (pin 2 and pin 4) to the 1.8V external
supply source. See Figure 2-2 for proper placement pin.
1.1V Analog Power Feedback Output. A 1 μF capacitor (Ceramic preferred), should be placed close to
VA11_PFBOUT 10 O
the VA11_PFBOUT.
In single supply operation this pin should be connected to VA11_PFBIN1 and V11_PFBIN2 (pin 1 and
pin 7). See Figure 2-1 for proper placement pin.
In multiple supply operation, when supplying 1.1V from external supply, this pin should be connected
together with VDD33_VA11 (pin 11), V11_PFBIN1 and V11_PFBIN2 (pin 1 and pin 7) to 1.1V external
supply source. See Figure 2-3 for proper placement pin.
1.8V Power Feedback Input. These pins are fed with power from V18_PFBOUT (pin 40) in single supply
V18_PFBIN1 2
operation.
I
1.8V from external source in multiple supply operation. A small 1μF capacitor should be connected close
V18_PFBIN2 4
to each pin.
1.1V Analog Power Feedback Input. These pins are fed with power from: VA11_PFBOUT (pin 10) in
VA11_PFBIN1 1
single supply operation.
I
1.1V from external source in multiple supply operation. A small capacitor of 0.1 μF should be connected
VA11_PFBIN2 7
close to each pin.
VDD11 20 O 1.1V Core Power Output. A capacitor of 1μF (Ceramic preferred) , should be placed close to the VDD11
17
VDD33_IO P I/O 3.3V Supply
29
External supply input to 1.1V analog regulator
VDD33_VA11 11 P This pin should be connected to 3.3V or 2.5V external supply, in single supply operation.
In multiple supply operation this pin should be connected to external 1.1V supply source.
External supply input to 1.8V regulator
VDD33_V18 41 P In single supply operation, this pin should be connected to a 3.3V or 2.5V external supply. In multiple
supply operation this pin should be connected to an external 1.8V supply source.
External supply input to 1.1V Core regulator
VDD33_VD11 21 P This pin should be connected to 3.3V or 2.5V external supply, in single supply operation.
In multiple supply operation this pin should be connected to external 1.1V supply source.
VSS 38 P Ground pin for Oscillator
GNDPAD 49 P Ground Pad
Copyright © 2009, Texas Instruments Incorporated Pin Descriptions 9
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