Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
2.7 Jumper Options
Jumper option is an elegant way to configure the TLK100 into specific modes of operation. Some of the
functional pins are used as jumper options. The logic states of these pins are sampled during reset and
are used to configure the device into specific modes of operation. Below table shows the pins used for the
jumper option and its description. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default jumper option. If the default
option is required, then there is no need for external pull-up or pull down resistors. Since these pins may
have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.
PIN TYPE
NAME NO. DESCRIPTION
PHYAD0 (MII_COL) 24
The TLK100 provides five PHY address pins, the states of which are latched into an
PHYAD1 (MII_RXD_0) 25
internal register at system hardware reset. The TLK100 supports PHY Address jumpering
PHYAD2 (MII_RXD_1) 26 S, O, PD
values 0 (<00000>) through 31 (<11111>). All PHYAD[4:0] pins have weak internal
PHYAD3 (MII_RXD_2) 27
pull-down resistors.
PHYAD4 (MII_RXD_3) 28
AN_EN: When high, this puts the part into advertised Auto-Negotiation mode with the
capability set by AN_0 and AN_1 pins. When low, this puts the part into Forced Mode with
the capability set by AN_0 and AN_1 pins.
AN_0 / AN_1: These input pins control the forced or advertised operating mode of the
TLK100 according to the following table. The value on these pins is set by connecting the
input pins to GND (0) or VCC (1) through 2.2 kΩ resistors. These pins should NEVER be
connected directly to GND or VCC.
The status of these pins are latched into the Basic Mode Control Register and the
Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
AN_EN AN_1 AN_0 Forced Mode
AN_EN (LED_ACT) 34
AN_1 (LED_SPEED) 35 S, O, PU
0 0 0 10BASE-T, Half-Duplex
AN_0 (LED_LINK) 36
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN_1 AN_0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 10BASE-TX, Half/Full-Duplex
10BASE-T, Half-Duplex
1 1 0
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
1 1 1
100BASE-TX, Half/Full-Duplex
This jumpering option along with LEDCR register bit determines the mode of operation of
LED_CFG (MII_CRS) 22 S, O, PU the LED pins. Default is Mode 1. All modes are also configurable via register access. See
the table in the LED Interface Section.
This jumpering option sets the Auto-MDIX mode. By default it enables MDIX. An external
MDIX_EN (MII_RX_ERR) 31 S, O, PU
pull-down will disable Auto-MDIX mode.
8 Pin Descriptions Copyright © 2009, Texas Instruments Incorporated
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