Datasheet

IDLE
(J/K)
Data
t
1
CRS
PMDInputPair
RXD[3:0]
RX_DV
RX_ER
T0346-01
t
2
DATA
(T/R)
IDLE
PMDInputPair
CRS
T0347-01
t
1
TLK100
www.ti.com SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
Table 9-9. 100BASE-TX Receive Packet Latency Timing
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
t
1
Carrier Sense ON Delay
(2)
100 Mb/s Normal mode 13.6 bits
(3)
t
2
Receive Data Latency 100 Mb/s Normal mode 18.4 bits
(1) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
(2) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(3) 1 bit time = 10 ns in 100 Mb/s mode
Figure 9-9. 100BASE-TX Receive Packet Latency Timing
Table 9-10. 100BASE-TX Receive Packet Deassertion Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Carrier Sense OFF Delay
(1)
100 Mb/s Normal mode 13.6 bits
(2)
(1) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100 Mb/s mode
Figure 9-10. 100BASE-TX Receive Packet Deassertion Timing
Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 75
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