Datasheet

TX_CLK
TXD
TX_EN
PMD Output Pair
(T/R)DATA IDLE
(T/R)
DATA
IDLE
T0344-01
t
1
PMD Output Pair
+1 rise
+1fall
–1fall
–1 rise
90%
10%
10%
90%
PMDOutput Pair
EyePattern
T0345-01
t
1
t
1
t
1
t
1
t
2
t
2
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009 www.ti.com
Table 9-7. 100BASE-TX Transmit Packet Deassertion Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_CLK to PMD Output Pair deassertion 100 Mb/s Normal mode 8.6 bits
Figure 9-7. 100BASE-TX Transmit Packet Latency Timing
Table 9-8. 100BASE-TX Transmit Timing (t
R/F
and Jitter)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
100 Mb/s PMD Output Pair t
R
and t
F
(1)
3 4 5 ns
t
1
100 Mb/s t
R
and t
F
Mismatch
(2)
500 ps
t
2
100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns
(1) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
(2) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
Figure 9-8. 100BASE-TX Transmit Timing (t
R/F
and Jitter)
74 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated
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