Datasheet

V
CC
XIClock
Hardware
RESET_N
DualFunctionPins
BecomeEnabled AsOutputs
Input
Output
T0338-01
t
1
t
2
V
CC
XIClock
Hardware
RESET_N
T0339-01
t
1
TLK100
www.ti.com SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
9.6 AC Specifications
Table 9-1. Power Up Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Reset deassertion time from power up 200 μs
Time from reset deassertion to the hardware Hardware Configuration Pins are described in
t
2
46 ns
configuration pins transition to output drivers the Pin Description section.
Figure 9-1. Power Up Timing
NOTE
It is important to choose pull-up and/or pull-down resistors for each of the hardware
configuration pins that provide fast RC time constants in order to latch-in the proper value
prior to the pin transitioning to an output driver.
Table 9-2. Reset Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
XI Clock must be stable for at min. of 1ms
t
1
RESET pulse width 1 μs
during RESET pulse low time.
Figure 9-2. Reset Timing
Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 71
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