Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
9.4 DC CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IH
Input high voltage
(1)
2.0 V
V
IL
Input low voltage
(1)
0.8 V
I
IH
Input high current V
IN
= V
CC
10 μA
I
IL
Input low current V
IN
= GND 10 μA
V
OL
Output low voltage I
OL
= 4 mA 0.4 V
V
OH
Output high voltage I
OH
= –4 mA V
CC
– 0.5 V
I
OZ
3-State leakage V
OUT
= V
CC
, V
OUT
= GND ±10 μA
V
TPTD_100
100M transmit voltage 0.95 1 1.05 V
V
TPTDsym
100M transmit voltage symmetry ±2%
V
TPTD_10
10M transmit voltage 2.2 2.5 2.8 V
C
IN1
CMOS input capacitance 5 pF
COUT1 CMOS output capacitance 5 pF
mV diff
SD
THon
100BASE-TX Signal detect turnon threshold 1000
pk-pk
mV diff
SD
THoff
100BASE-TX Signal detect turnoff threshold 200
pk-pk
V
TH1
10BASE-T Receive threshold 585 mV
(1) Nominal V
CC
of VDD33_IO = 3.3V
9.5 POWER SUPPLY CHARACTERISTICS
The data was measured from a TLK100 evaluation board. The current from each of the power supply is
measured and the power dissipation is computed. For the single 3.3V external supply case the power dissipation
across the internal linear regulator is also included. All the power dissipation numbers are measured at the
nominal power supply and typical temperature of 25°C.
9.5.1 Active Power
PARAMETER TEST CONDITIONS FROM THE FROM THE UNIT
POWER SUPPLIES CENTER TAP
Multiple External Supplies 146 43
100BASE-T /W Traffic (full packet 1518B rate)
Single 3.3V external supply 316 80
mW
Multiple External Supplies 84 205
10BASE-T /W Traffic (full packet 1518B rate)
Single 3.3V external supply 189 205
9.5.2 Power Down Power
PARAMETER TEST CONDITIONS FROM THE POWER SUPPLIES UNIT
Multiple External Supplies 14.2
Extreme Low Power Mode
Single 3.3V external supply 23.1
Multiple External Supplies 18.2
General Power Down Mode
(1)
Single 3.3V external supply 33
mW
Multiple External Supplies 51.4
Passive Sleep Mode
Single 3.3V external supply 102.3
Multiple External Supplies 51.4
Active Sleep Mode
Single 3.3V external supply 102.3
(1) The internal PLL is disabled. System works of the Refclk
70 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated
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