Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History

TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
9 Electrical Specifications
All parameters are derived by test, statistical analysis, or design.
9.1 ABSOLUTE MAXIMUM RATINGS
(1)
VALUE UNIT
VDD33_IO, VDD33_VA11, Supply voltage –0.3 to 3.8 V
VDD33_V18, VDD33_VD11
V18_PFBIN1, V18_PFBIN2 –0.3 to 2.2 V
VA11_PFBIN1, VA11_PFBIN2 –0.3 to 1.8 V
XI DC Input voltage –0.3 to 2.2 V
TD-, TD+, RD-, RD+ –0.3 to 6 V
Other Inputs –0.3 to 3.8 V
XO DC Output voltage –0.3 to 2.2 V
Other outputs –0.3 to 3.8 V
Maximum die temperature θ
J
105 °C
IEC 60749-26 ESD (human-body model)
(2)
±16 kV
JEDEC Standard 22, Test Method A114 (human-body model)
(2)
±16
ESD
JEDEC Standard 22, Test Method A114 (human-body model), all pins 1.5
JEDEC Standard 22, Test Method C101 (charged-device model), all pins 1.5
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) On pins TD+, TD-, RD+, RD-, with VDD33_IO, VDD33_VA11 VDD33_V18, VDD33_VD11, V18_PFBIN1, V18_PFBIN2, VA11_PFBIN1,
VA11_PFBIN2, VA11_PFBOUT, V18_PFBOUT, VDD11, VSS connected to ground potential.
9.2 THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
θ
JA
Junction-to-ambient thermal resistance (no airflow) 26.8
θ
JB
Junction-to-board thermal resistance 16.2 °C/W
θ
JC
Junction-to-case thermal resistance 40
9.3 RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VDD33_VA11,VDD33_V18, Core Supply voltage 2.38 3.3 3.6 V
VDD33_VD11
VDD33_IO I/O 3.3V Supply 3.0 3.3 3.6 V
V18_PFBIN1, External Supply
(1)
1.7 1.8 1.9 V
V18_PFBIN2
VA11_PFBIN1, 1.04 1.1 1.15 V
VA11_PFBIN2
T
A
Ambient temperature
(2)
–40 85 °C
P
D
Power dissipation
(3)
189 mW
(1) When the internal voltage regulator is not used and the external supply is used
(2) Provided that GNDPAD, pin 49, is soldered down. See Thermal Vias Recommendation for more detail.
(3) For 100Base-TX, When external 1.8V, 1.1 and 3.3V supplies are used.
Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 69
Submit Documentation Feedback
Product Folder Link(s): TLK100