Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
This register allows configuring the gear threshold values for the TDR test.
Table 8-48. TDR Pattern Control Register 2 (TDRLCR2), address 0x0C0C
BIT NAME DEFAULT FUNCTION
15:9 Reserved 0,RO Ignore on read
8:4 cfg_ptrn_gear_tout 0x14,RW Thresholds gear shifts distance in samples
3:0 Reserved 0x8,RO Ignore on read
8.5.20 DSA Configuration Register 1 (DSACR1)
This register allows use of the smoothing filter during the DSA tests.
Table 8-49. DSA Configuration Register 1 (DSACR1), address 0x0C26
BIT NAME DEFAULT FUNCTION
15:7 Reserved 0x180,RO Ignore on read
6 cfg_dsa_smooth_filt_byps 0x1,RW 0 = Disable DSA engine smooth filter bypass
1 = Enable DSA engine smooth filter bypass
5:0 Reserved 0x04,RO Ignore on read
8.5.21 DSA Configuration Register 2 (DSACR2)
This register allows configuration of the DSA taps are used for the DSA tests. We specify the first and last
taps in use and the DSA uses all the taps between them.
Table 8-50. DSA Configuration Register 2 (DSACR2), address 0x0C27
BIT NAME DEFAULT FUNCTION
15:8 cfg_dsa_en_last_coeff_num 0x1E,RW Last coefficient number used by the DSA engine
7:0 cfg_dsa_en_first_coeff_num 0x0,RW First coefficient number used by the DSA engine
8.5.22 DSA Start Frequency (DSASFR)
This register allows configuration of the starting frequency for the spectrum analysis of the DSA engine. It
represents 1.9 kHz resolution in the frequency domain.
Table 8-51. DSA Start Frequency (DSASFR), address 0x0C28
BIT NAME DEFAULT FUNCTION
15:0 cfg_start_freq 0x0,RW Starting frequency for the DSA
8.5.23 DSA Frequency Control (DSAFCR)
This register defines the average factor we will use in the DSA. In addition it defines the frequency step for
the DSA. The field represents resolution of 119.2 Hz.
Table 8-52. DSA Frequency Control (DSAFCR), address 0x0C29
BIT NAME DEFAULT FUNCTION
15:12 cfg_dsa_average 0xA,RW Averaging factor for DSA engine – 2X cycles
11 Reserved 0x0,RO Reserved
10:0 cfg_dsa_inc_factor 0x400,RW DSA Frequency increment factor (frequency step)
66 Register Block Copyright © 2009, Texas Instruments Incorporated
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