Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
8.5.8 TDR Control Register (TDRCR)
This register allows configuring the TDR modes.
Table 8-37. TDR Control Register (TDRCR), address 0x0C01
BIT NAME DEFAULT FUNCTION
15:11 Reserved 0x02,RO Ignore on read
10 cfg_tdr_tx_mode 0x1,RW 1 – Enable TDR TX transmission mode
9 Reserved 0,RW Reserved
8:6 cfg_soft_avr_cycles 0x7,RW Number of averaging cycles:
0x0 – TDR disabled.
0x1 – 1 TDR cycle (no averaging).
0x2 – 2 TDR cycles.
0x3 – 4 TDR cycles.
0x4 – 8 TDR cycles.
0x5 – 16 TDR cycles.
0x6 – 32 TDR cycles.
0x7 – 64 TDR cycles.
5:3 cfg_post_cmp_size 0x4,RW Number of forward samples for peak detection comparison.
2:0 cfg_pre_cmp_size 0x3,RW Number of backward samples for peak detection comparison.
8.5.9 TDR Clock Cycles Register (TDRLCR)
This register allows configuring the number of clock cycles in a pattern TDR test.
Table 8-38. TDR Clock Cycles Register (TDRLCR), address 0x0C02
BIT NAME DEFAULT FUNCTION
15:8 Reserved 0,RO Ignore on read
7:0 cfg_ptrn_cycle_time 0xFF,RW Number of clock cycles in a TDR pattern test.
8.5.10 TDR Low Threshold Register (TDRLT1)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-39. TDR Low Threshold Register (TDRLT1), address 0x0C03
BIT NAME DEFAULT FUNCTION
15 Reserved 0,RO Ignore on read
14:8 cfg_ptrn_low_th_1 0xC,RW Peak (absolute) low threshold value 1, for TX pattern.
7 Reserved 0,RO Ignore on read
6:0 cfg_ptrn_low_th_0 0x10,RW Peak (absolute) low threshold value 0, for TX pattern.
8.5.11 TDR Low Threshold Register (TDRLT2)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-40. TDR Low Threshold Register (TDRLT2), address 0x0C04
BIT NAME DEFAULT FUNCTION
15 Reserved 0,RO Ignore on read
14:8 cfg_ptrn_low_th_3 0x7,RW Peak (absolute) low threshold value 3, for TX pattern.
7 Reserved 0,RO Ignore on read
6:0 cfg_ptrn_low_th_2 0x9,RW Peak (absolute) low threshold value 2, for TX pattern.
Copyright © 2009, Texas Instruments Incorporated Register Block 63
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