Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
8.5.5 TDR Pattern Amplitude Register (TDRPAR)
This register allows to program the pattern used to generate the TDR pulses. Bits 4:0 of this register give
the amplitude of the TDR pulse. A value of 0x8 maps to an amplitude of 1V. For values from 0x8 to 0xF
the amplitude is saturated to 1V. The TDR pattern is 16 symbols long. So, sixteen consecutive writes to
this register are required. The value of these bits for each write determines the amplitude for that symbol.
Each symbol is 8ns wide. For this register to function, the bits 15,14 of TDRSMR register (0x0080) should
be set to ‘1’
Table 8-34. TDR Pattern Amplitude Register (TDRPAR), address 0x0090
BIT NAME DEFAULT FUNCTION
15:5 Reserved 0,RO Ignore on read
4:0 tdr_pattern_din_config 0,RW Configure TDR Transmit Pattern.
8.5.6 TDR Manual Pulse Register (TDRMPR)
This register allows to program a manual TDR pulse. When bit 1 of this register is set then the pattern
programmed in the TDRPAR register is put on the TD line. If the TDRPAR register is not programmed
then a default TDR pulse is put on the TD line. It is NOT used for TDR measurements.
Table 8-35. TDR Manual Pulse Register (TDRMPR), address 0x0094
BIT NAME DEFAULT FUNCTION
15:2 Reserved 0,RO Ignore on read
1 tdr_tx_start 0,RW 1 = Start TDR pattern transmission
0 = Do not start TDR pattern transmission
0 Reserved 0x0,RW Reserved
8.5.7 TDR Channel Silence Register (TDRCSR)
This register allows programming of the TDR channel silence timers.
Table 8-36. TDR Channel Silence Register (TDRCSR), address 0x0C00
BIT NAME DEFAULT FUNCTION
15:14 Reserved 0,RO Ignore on read
13:12 cfg_link_down_timer 0x2,RW Hold time, to make sure the link failed:
0x0 – no hold time.
0x1 – 500ms hold time.
0x2 – 1s hold time.
0x3 – 2s hold time.
11:10 cfg_post_silence_time 0x1,RW The needed silence time after the TDR test:
0x0 – no silence needed.
0x1 – 10ms of silence.
0x2 – 100ms of silence.
0x3 – 1s of silence.
9:8 cfg_pre_silence_time 0x1,RW The needed silence time before the TDR test:
0x0 – no silence needed.
0x1 – 10ms of silence.
0x2 – 100ms of silence.
0x3 – 1s of silence.
7:0 cfg_silence_th 0xC8,RW Energy calculator threshold value, to break silence.
62 Register Block Copyright © 2009, Texas Instruments Incorporated
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