Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
8.5.2 Cable Diagnostic Status Register (CDSR)
This register gives the status of the cable diagnostic tests. It also allows configuring different modes of the
ALCD and DSA tests.
Table 8-31. Cable Diagnostic Status Register (CDSR), address 0x001B
BIT NAME DEFAULT DESCRIPTION
15 ALCD/DSA Done 0,RO 1 = ALCD/DSA is done
0 = ALCD/DSA is not done
14 TDR Fail 1,RO 1 = TDR has failed
0 = TDR has not failed
13 TDR Done 0,RO 1 = TDR is done
0 = TDR is not done
12:10 Reserved 0x4,RO Ignore on read
9:6 DSA Input Signal 7,RW 7 = ALCD
5 = DSA Adaptive data mode
3 = DSA Raw data mode
Others are reserved
5 DSA Enable 0,RW 1 = DSA Engine is enabled
0 = DSA Engine is disabled
4 ALCD/DSA mode 1,RW 1 = DSA Raw data mode
0 = ALCD/DSA Adaptive data mode
3:0 Reserved 0,RO Ignore on read
8.5.3 Cable Diagnostic Results Register (CDRR)
This register gives the result of the cable diagnostic tests. The software will post process this result.
Table 8-32. Cable Diagnostic Results Register (CDRR), address 0x001C
BIT BIT NAME DEFAULT DESCRIPTION
15:0 Cable Diagnostics Result Register 0, RO As specified in register 0x1A bits [11:8]
8.5.4 TDR State Machine Enable (TDRSMR)
This register allows configuration of the TDR state machines. Only when the bits 15, 14 of this register are
set to ‘1’ the registers 0x0090 and 0x0094 can be used.
Table 8-33. TDR State Machine Enable Register (TDRSMR), address 0x0080
BIT NAME TYPE RESET FUNCTION
15 cmn_tdr_sm_mode RW 0 1 = Configure TDR state machine mode. This bit is cleared when TDR is complete
14 cmn_tdr_tx_sm_m RW 0 1 = Configure TDR transmit state machine mode. This bit is cleared when the TDR is
ode complete.
13:0 Reserved RW 0 Reserved
Copyright © 2009, Texas Instruments Incorporated Register Block 61
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