Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
8.4.15 False Carrier Sense Counter Register (FCSCR)
This register counts the error nibbles between the IDLE nibbles (BAD_SSD), in nibble time. This count
register is reset when this register is read.
Table 8-28. False Carrier Sense Counter Register (FCSCR), address 0x0042
BIT BIT NAME DEFAULT DESCRIPTION
15:8 RESERVED 0, RO Ignore on read
7:0 idle_err_count_100 0, RO IDLE error counter value. Counts received error nibbles between IDLE nibbles (BAD_SSD), in
nibble time.
Note: Reading this register clears the idle_err_count_100 counter
8.4.16 RX Channel Control Register (RXCCR)
This register allows configuration of RX channel. By programming bits 3,2 of this register to ‘1’ the
channels can be mirrored.
Table 8-29. RX Channel Control Register (RXCCR), address 0x0070
BIT NAME DEFAULT FUNCTION
15:4 Reserved 0,RO Ignore on read
3 Polarity_inv 0,RW When 1 Change the polarity of:
1 = Polarity of RD and TD is inverted
0 = Polarity of RD and TD is not inverted
2 Mdix 0,RW 1 = MDIX
0 = MDI
1:0 Reserved 0,RW Always write 0
8.5 Cable Diagnostic Registers
8.5.1 Cable Diagnostic Registers (CDCR)
This register is used to select the channel for which cable diagnostics test needs to be done. It has the
enable bits for the diagnostic tests and also allows one to choose which TDR peak and location will be
written to the CDRR register (0x001C).
Table 8-30. Cable Diagnostic Registers (CDCR), address 0x001A
BIT NAME DEFAULT DESCRIPTION
15:14 Reserved 0,RW, SC Always 0
13 ALCD/DSA Test 0,RW, SC 1 = Start ALCD/DSA test.
Start 0 = Do not start ALCD/DSA test
12 TDR Test Start 0,RW, SC 1 = Start TDR test
0 = Do not start TDR test
11 Reserved 0,RO Reserved
10:8 Cable Diagnostics 0,RW Selects the output of register 0x1C as follows:
Result Select 0: {TDR peak 0 amplitude, TDR peak 0 location}
1: {TDR peak 1 amplitude, TDR peak 1 location}
2: {TDR peak 2 amplitude, TDR peak 2 location}
3: {TDR peak 3 amplitude, TDR peak 3 location}
4: {TDR peak 4 amplitude, TDR peak 4 location}
6: ALCD Length
8:1 Reserved 0,RO Ignore on read
0 Channel Select 0,RW Selects channel for Cable Diagnostics Test
0 = TD±
1 = RD±
60 Register Block Copyright © 2009, Texas Instruments Incorporated
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