Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
8.4.6 Receiver Error Counter Register (RECR)
This counter keeps count of the number of receive errors.
Table 8-19. Receiver Error Counter Register (RECR), address 0x0015
BIT BIT NAME DEFAULT DESCRIPTION
15:0 RX Error Count 0, RO, SC Receive errors counter (saturates in max value, clears on dummy write)
8.4.7 BIST Control Register (BISCR)
This register is used for configuring the PRBS BIST and to select the loopback point in the signal chain.
Table 8-20. BIST Control Register (BISCR), address 0x0016
BIT NAME DEFAULT DESCRIPTION
15 PRBS Count Mode 0, RW 1 = Continuous mode, when on of the PRBS counters reaches max value, pulse is
generated and counter starts counting from zero again
0 = Single mode, When one of the PRBS counters reaches it's max value, PRBS
checker stops counting.
14 Generate PRBS Packets 0, RW 1 = When packet generator is enabled, generate continuous packets with PRBS data.
When packet generator is disabled, PRBS checker is still enabled.
0 = When packet generator is enabled, generate single packet with constant data.
PRBS gen/check is disabled.
13 Packet Generation 64 bit 0, RW 1 = Transmit 64 byte packets in packet generation mode
mode
0 = Transmit 1518 byte packets in packet generation mode
12 Packet Generation Enable 0, RW 1 = Enable packet/PRBS generator
0 = Disable packet/PRBS generator
11:5 Reserved 0, RO Ignore on read
4:0 Loopback Mode 0, RW Selects loop back mode:
Near-end Loopbacks
[00001] – MII Loopback
[00010] – PCS Loopback (In 100BaseTX only)
[00100] – Digital Loopback
[01000] – Analog Loopback (requires 100Ω termination)
Far-end Loopback:
[10000] – Reverse Loopback
8.4.8 BIST STATUS Register (BISSR)
This register gives the status of the PRBS test and the sleep mode of the core.
Table 8-21. BIST STATUS Register (BISSR), address 0x0017
BIT NAME DEFAULT DESCRIPTION
15:12 Reserved 0,RO Ignore on read
11 PRBS Locked 0,RO 1 = PRBS checker is locked on received byte stream
0 = PRBS checker is not locked
10 PRBS Sync Loss 0,RO,LH 1 = PRBS checker has lost sync
0 = PRBS checker has not lost sync
9 Packet Generator Busy 0,RO 1 = Packet generator is in process
0 = Packet generator is not in process
8 Core Power Mode 0,RO 1 = Core is in normal power mode
Status 0 = Core is powered down or in sleep mode
7:0 Reserved 0,RO Ignore on read
Copyright © 2009, Texas Instruments Incorporated Register Block 57
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