Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
8.4.4 MII Interrupt Status Register (MINTSR)
This register gives the status of the different interrupt function supported by TLK100.
Table 8-17. MII Interrupt Status Register (MINTSR), address 0x0013
BIT NAME DEFAULT DESCRIPTION
15 Auto-Negotiation Error 0, RO, LH 1 = Auto-Negotiation error has occurred
0 = Auto-Negotiation error has not occurred
14 Speed Changed 0,RO, LH 1 = Link speed has changed
0 = Link speed has not changed
13 Duplex Mode Changed 0,RO, LH 1 = Duplex mode has changed
0 = Duplex mode has not changed
12 Page Received 0,RO, LH 1 = Page has been received
0 = Page has not been received
11 Auto-Negotiation Completed 0,RO, LH 1 = Auto-Negotiation has completed
0 = Auto-Negotiation has not completed
10 Link Status Changed 0,RO, LH 1 = Link status has changed
0 = Link status has not changed
9:8 Reserved 0,RO Ignore on read
7 FIFO Overflow/Underflow 0,RO, LH 1 = FIFO Overflow/Underflow occurred
0 = FIFO Overflow/Underflow did not occur
6 MDI Crossover Changed 0,RO, LH 1 = MDI crossover has changed
0 = MDI crossover has not changed
5 Reserved 0,RO Ignore on read
4 Sleep Mode Changed 0,RO, LH 1 = Sleep mode has changed
0 = Sleep mode has not changed
3:2 Reserved 0,RO Ignore on read
1 Polarity Changed 0,RO, LH 1 = Data polarity has changed
0 = Data polarity has not changed
0 Jabber 0,RO, LH 1 = Jabber detected
0 = Jabber not detected
8.4.5 MII Interrupt Control Register (MINTCR)
This register enables to control the polarity and enabling the interrupts.
Table 8-18. MII Interrupt Control Register (MINTCR), address 0x0014
BIT NAME DEFAULT DESCRIPTION
15 INTN_OE 0,RW Bit 15 Bit 12 Pin 42 Function
0 0 Power Down
0 1 Power Down
1 0 Interrupt
1 1 Power Down
14 Reserved 0,RO Ignore on read
13 Interrupt Polarity 1,RW 1 = Interrupt pin is active low
0 = Interrupt pin is active high
12 INTN_OEN 1,RW Refer to the table given in the bit 15 description.
11:0 Reserved 0,RO Ignore on read
56 Register Block Copyright © 2009, Texas Instruments Incorporated
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