Datasheet

TLK100
www.ti.com SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
8.4 Extended Registers
8.4.1 PHY Control Register (PHYCR)
This register provides quick access to commonly accessed PHY control information.
Table 8-14. PHY Control Register (PHYCR), address 0x0010
BIT BIT NAME DEFAULT DESCRIPTION
15:14 TX FIFO Depth 0x1,RW 00 = 4 nibbles
01 = 5 nibbles
10 = 6 nibbles
11 = 8 nibbles
13:12 Reserved 0,RO Ignore on read
11 Reserved 0,RO Ignore on read
10 Force Link Good 0,RW 1 = Force link_ctrl_en10/100 according to selected speed in register 0x0
0 = Do Normal operation
9:8 Power Down 00,RW 00 = Normal mode
Mode
01 = General Power Down mode: Besides SMI module everything is powered down, if bit [4]
set to ’1’, PLL is also powered down. When PLL is powered down, Reference clock is
used.
10 = Active Sleep mode – same as passive sleep, but also send NLP every ~1.4 Sec to wake
up link-partner. Automatic power-up is done when link partner is detected.
11 = Passive Sleep Mode - Besides SMI and energy detect modules, everything is powered
down. Automatic power-up is done when link partner is detected.
Bit 11 of the BMCR register(0x00) to '1' for all of these power down modes.
7 Reserved 0,RW Reserved
6 Auto MDI-X SOR,RW 1 = Enable automatic crossover
Enable
0 = Disable automatic crossover
5 Manual MDI-X 0,RW 0 = Manual MDI configuration
Mode
1 = Manual MDI-X configuration
4 Disable PLL 0,RW 1 = Disable PLL
0 = Enable PLL
3:1 Reserved 0,RO Ignore on read
0 Disable Jabber 0,RW 1 = Disable Jabber function
0 = Enable Jabber function
Copyright © 2009, Texas Instruments Incorporated Register Block 53
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