Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
8.1.2 Basic Mode Status Register (BMSR)
Table 8-4. Basic Mode Status Register (BMSR), address 0x0001
BIT BIT NAME DEFAULT DESCRIPTION
15 100BASE-T4 0, RO/P 100BASE-T4 Capable:
This protocol is not available. Always 0 = Device does not perform 100BASE-T4 mode.
14 100BASE-TX 1, RO/P 100BASE-TX Full Duplex Capable:
Full Duplex
1 = Device able to perform 100BASE-TX in full duplex mode.
0 = Device not able to perform 100BASE-TX in full duplex mode.
13 100BASE-TX 1, RO/P 100BASE-TX Half Duplex Capable:
Half Duplex
1 = Device able to perform 100BASE-TX in half duplex mode.
0 = Device not able to perform 100BASE-TX in half duplex mode.
12 10BASE-T 1, RO/P 10BASE-T Full Duplex Capable:
Full Duplex
1 = Device able to perform 10BASE-T in full duplex mode.
0 = Device not able to perform 10BASE-T in full duplex mode.
11 10BASE-T 1, RO/P 10BASE-T Half Duplex Capable:
Half Duplex
1 = Device able to perform 10BASE-T in half duplex mode.
0 = Device not able to perform 10BASE-T in half duplex mode.
10: RESERVED 0, RO RESERVED: Write as 0, read as 0.
7
6 MF Preamble 1, RO/P Preamble suppression Capable:
Suppression
1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble
needed only once after reset, invalid opcode or invalid turnaround.
0 = Device will not perform management transaction with preambles suppressed.
5 Auto- 0, RO Auto-Negotiation Complete:
Negotiation
1 = Auto-Negotiation process complete.
Complete
0 = Auto-Negotiation process not complete (either still in process, disabled, or reset)
4 Remote Fault 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault
Indication or notification from Link Partner of Remote Fault.
0 = No remote fault condition detected.
3 Auto- 1, RO/P Auto Negotiation Ability:
Negotiation
1 = Device is able to perform Auto-Negotiation.
Ability
0 = Device is not able to perform Auto-Negotiation.
2 Link Status 0, RO/LL Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber. condition detected.
0 Extended 1, RO/P Extended Capability:
Capability
1 = Extended register capabilities.
0 = Basic register set capabilities only.
The PHY Identifier Registers #1 and #2 together form a unique identifier for the TLK100. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number
and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY
Identifier if desired. The PHY Identifier is intended to support network management. The IEEE-assigned
OUI for Texas Instruments is 080028h.
Copyright © 2009, Texas Instruments Incorporated Register Block 45
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