Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
8.1.1 Basic Mode Control Register (BMCR)
Table 8-3. Basic Mode Control Register (BMCR), address 0x0000
BIT BIT NAME DEFAULT DESCRIPTION
15 Reset 0, RW/SC PHY Software Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
Writing a 1 to this bit causes the PHY to be reset. When the reset operation is done, this bit
is cleared to 0 automatically. The configuration is relatched.
14 Loopback 0, RW Loopback:
1 = Loopback enabled.
0 = Normal operation.
When loopback mode is activated, the transmitter data presented on TXD is looped back to
RXD internally
13 Speed Selection Jumper, RW Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100 Mb/s
0 = 10 Mb/s
12 Auto-Negotiation Jumper, RW Auto-Negotiation Enable:
Enable
Configuration pin (jumper) controls initial value at reset.
1 = Auto-Negotiation Enabled – bits 8 and 13 of this register are ignored when this bit is
set.
0 = Auto-Negotiation Disabled – bits 8 and 13 determine the port speed and duplex
mode.
11 Power Down 0, RW Power Down:
1 = Enables Power Down Modes - General Power Down Mode, Active Sleep Mode and
Passive Sleep Mode (see register 0x10)
0 = Normal operation.
10 Isolate 0, RW Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
9 Restart Auto- 0, RW/SC Restart Auto-Negotiation:
Negotiation
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If
Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing
and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will
self-clear. Operation of the Auto-Negotiation process is not affected by the
management entity clearing this bit.
0 = Normal operation.
Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit
is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is
initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected
by the management entity clearing this bit.
8 Duplex Mode Jumper, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be
selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled.
0 = Normal operation
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.
44 Register Block Copyright © 2009, Texas Instruments Incorporated
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