Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
Table 8-2. Register Table (continued)
Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BIST Status Register 17h BISSR Reserved Reserved Reserved Reserved PRBS PRBS Sync PRBS Core Power Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Locked Loss Generator Mode
busy Status
BIST Byte Count 71h BISBCR PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS
Register Count Count Count Count Count Count Count Count Count Count Count Count Count Count Count Count
BIST Error Count 72h BISECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PRBS Error PRBS Error PRBS Error PRBS Error PRBS Error PRBS Error PRBS Error PRBS Error
Register Count Count Count Count Count Count Count Count
BIST Packet Length 7Bh BISPLR PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS
register Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet
Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length
BIST Inter Packet 7Ch BISIPGR PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG
Gap Register Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length
LED Control Register 18h LEDCR LED Pulse Width Pulse Width Force Reserved Reserved Blink Rate Blink Rate Reserved LED Mode LED Mode Reserved Reserved LED ACT LED LED LINK
Enable Interrupt Polarity SPEED Polarity
Polarity
Power Down Register 1Fh PDR Software Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Global
Reset
False Carrier Sense 42h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Idle_error_c Idle_error_c Idle_error_c Idle_error_c Idle_error_c Idle_error_c Idle_error_c Idle_error_c
Counter Register ount ount ount ount ount ount ount ount
RX Channel Control 70h RXCCR Rese-rved Rese-rved Rese-rved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Polarity Mdix Reserved Reserved
Register Inversion
Cable Diagnostic 1Ah CDCR Reserved Reserved ALCD/ DSA TDR test Reserved Cable Diag Cable Diag Cable Diag Reserved Reserved Reserved Reserved Reserved Reserved Reserved Channel
Register test start Start result result result Select
Select Select Select
Cable Diagnostic 1Bh CDSR ALCD/ DSA TDR Fail TDR Done Reserved Reserved Reserved DSA Input DSA Input DSA Input DSA Input DSA ALCD/ DSA Reserved Reserved Reserved Reserved
Status Register Done Signal Signal Signal Signal Enalbe mode
Cable Diagnostic 1Ch CDRR Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag Cable Diag
Results Register Results Results Results Results Results Results Results Results Results Results Results Results Results Results Results Results
TDR State Machine 80h TDRSMR Cmn_tdr_ Cmn_tdr Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Enable sm_mode _tx_sm_
mode
TDR Pattern 90h TDRPAR Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved TDR TDR TDR TDR TDR
Amplitude Register pattern pattern pattern pattern pattern
TDR Manual Pulse 94h TDRMPR Rese-rved Rese-rved Rese-rved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TDR_TX Reserved
Register _START
TDR Algorithm
0C00h – 0C0Ch
Registers
ALCD/DSA Registers 0C26h – 0C2Ah
Cable Diagnostic algorithm related registers
CD Pre test 0107h, 010Fh
Configuration
LPF Bypass Register 00ACh
42 Register Block Copyright © 2009, Texas Instruments Incorporated
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