Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
Table 8-2. Register Table
Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Basic Mode Control 00h BMCR Reset Loopback Speed Auto-Neg Power Isolate Restart Duplex Collision Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Selection Enable Down Auto-Neg Mode Test
Basic Mode Status 01h BMSR 100Base 100Base 100Base 10Base-T 10Base-T Reserved Reserved Reserved Reserved MF Auto-Neg Remote Auto-Neg Link Status Jabber Extended
Register -T4 -TX FDX -TX HDX FDX HDX Preamble Complete Fault Ability Detect Capability
Suppress
PHY Identifier 02h PHYIDR 1 OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB
Register 1
PHY Identifier 03h PHYIDR 2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ MDL_ REV MDL_ REV MDL_ REV MDL_ REV
Register 2 MDL MDL MDL MDL MDL MDL
Auto-Negotiation 04h ANAR Next Page Reserved Remote Reserved ASM_DI R PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol
Advertisement Ind Fault Selection Selection Selection Selection Selection
Register
Auto-Negotiation Link 05h ANLPAR Next Page ACK Remote Reserved ASM_DI R PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol
Partner Ability Ind Fault Selection Selection Selection Selection Selection
Register (Base Page)
Auto-Negotiation 06h ANER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_ NP_ ABLE PAGE_ RX LP_AN_AB
Expansion Register ABLE LE
Auto-Negotiation Next 07h ANNPTR Next Page Reserved Message ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
Page TX Register Ind Page
Auto-Negotiate Link 08h ANLNPTR Next Page Reserved Message ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
Partner Ability Page Ind Page
Register
RESERVED 09-0Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Control 0Dh REGCR Function Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DEVICE DEVICE DEVICE DEVICE DEVICE
Register ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS
Address or Data 0Eh ADDAR Addr/ Data Addr/ Data Addr /Data Addr /Data Addr/ Data Addr/ Data Addr /Data Addr /Data Addr/ Data Addr/ Data Addr /Data Addr /Data Addr/ Data Addr/ Data Addr /Data Addr /Data
Register
RESERVED 0Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXTENDED REGISTERS
PHY Control Register 10h PHYCR TX FIFO TX FIFO Reserved Reserved Reserved Force Link Power Power Reserved Auto MDI-X Manual Disable Reserved Reserved Reserved Disable
Depth Depth Good Down Mode Down Mode Enable MDI-X PLL Jabber
Enable
PHY Status Register 11h PHYSR Reserved Speed Duplex Page Auto Nego Link Status Reserved MDI Cross Reserved Sleep Reserved Reserved Reserved Reserved Polarity Jabber
Received Complete over Mode
MII Interrupt Mask 12h MINTMR Auto Nego Speed Duplex Page Auto Nego Link Status Reserved Reserved FIFO Over MDI cross Reserved Sleep Reserved Reserved Polarity Jabber
Register error Change Mode Received Complete Change Under flow over Mode Change Interrupt
Enable Enable Change Enable Enable Enable Enable change Change Enable Enable
Enable Enable Enable
MII Interrupt Status 13h MINTSR Auto Nego Speed Duplex Page Auto Nego Link Status Reserved Reserved FIFO Over MDI Reserved Sleep Reserved Reserved Polarity Jabber
Register Error Changed Mode Received Complete Changed Underflow Crossover Mode Changed
Changed Changed Changed
MII Interrupt Control 14h MINTCR Interrupt Reserved Interrupt Interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Pin Enable Polarity Pin Enable
Receive Error 15h RECR RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT
Counter Register
BIST Control Register 16h BISCR PRBS Generate 64 bit mode Packet Reserved Reserved Reserved Reserved Reserved Reserved Reserved Loopback Loop back Loop back Loop back Loop back
Count PRBS Generation Mode Mode Mode Mode Mode
Mode Packets Enable
Copyright © 2009, Texas Instruments Incorporated Register Block 41
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