Datasheet

TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009 www.ti.com
1 Introduction .............................................. 1 5.1 Transmit Path Encoder ............................. 26
5.2 Receive Path Decoder .............................. 28
1.1 Features .............................................. 1
5.3 10M Squelch ........................................ 30
1.2 Applications .......................................... 1
5.4 Auto MDI/MDI-X Crossover ........................ 31
1.3 General Description .................................. 1
5.5 Auto Negotiation .................................... 32
1.4 System Diagram ..................................... 1
6 Reset and Power Down Operation ................. 34
1.5 Pin Layout ............................................ 3
6.1 Hardware Reset .................................... 34
2 Pin Descriptions ......................................... 5
6.2 Software Reset ..................................... 34
2.1 Serial Management Interface ........................ 5
6.3 Power Down/Interrupt .............................. 34
2.2 MAC Data Interface .................................. 6
6.4 Power Down Modes ................................ 35
2.3 Clock Interface ....................................... 6
7 Design Guidelines ..................................... 36
2.4 LED Interface ........................................ 6
7.1 TPI Network Circuit ................................. 36
2.5 JTAG Interface ....................................... 7
7.2 Clock In (XI) Requirements ......................... 36
2.6 Reset and Power Down .............................. 7
7.3 Thermal Vias Recommendation .................... 38
2.7 Jumper Options ...................................... 8
8 Register Block ......................................... 39
8.1 Register Definition .................................. 43
2.8 10 Mb/s and 100 Mb/s PMD Interface ............... 9
8.2 Register Control Register (REGCR) ................ 52
2.9 Power and Bias Connections ........................ 9
8.3 Address or Data Register (ADDAR) ................ 52
2.10 Power Supply Configuration ........................ 10
8.4 Extended Registers ................................. 53
3 Configuration ........................................... 13
8.5 Cable Diagnostic Registers ......................... 60
3.1 Auto-Negotiation .................................... 13
9 Electrical Specifications ............................. 69
3.2 Auto-MDIX .......................................... 14
9.1 ABSOLUTE MAXIMUM RATINGS ................. 69
3.3 PHY Address ....................................... 15
9.2 THERMAL CHARACTERISTICS ................... 69
3.4 LED Interface ....................................... 16
9.3 RECOMMENDED OPERATING CONDITIONS .... 69
3.5 Loopback Functionality ............................. 17
9.4 DC CHARACTERISTICS ........................... 70
3.6 BIST ................................................ 18
9.5 POWER SUPPLY CHARACTERISTICS ........... 70
3.7 Cable Diagnostics .................................. 19
9.6 AC Specifications ................................... 71
4 Interfaces ................................................ 21
10 Appendix A: Digital Spectrum Analyzer (DSA)
4.1 Media Independent Interface (MII) ................. 21
Output .................................................... 83
4.2 Serial Management Interface ....................... 22
Revision History ............................................ 84
5 Architecture ............................................. 26
4 Contents Copyright © 2009, Texas Instruments Incorporated
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