Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
www.ti.com
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
8 Register Block
Table 8-1. Register Map
OFFSET HEX ACCESS TAG DESCRIPTION
00h RW BMCR Basic Mode Control Register
01h RO BMSR Basic Mode Status Register
02h RO PHYIDR1 PHY Identifier Register #1
03h RO PHYIDR2 PHY Identifier Register #2
04h RW ANAR Auto-Negotiation Advertisement Register
05h RO ANLPAR Auto-Negotiation Link Partner Ability Register
06h RO ANER Auto-Negotiation Expansion Register
07h RW ANNPTR Auto-Negotiation Next Page TX
08h RO ANLNPTR Auto-Negotiation Link Partner Ability Next Page Register
09h–0Ch RW RESERVED RESERVED
0Dh RW REGCR Register control register
0Eh RW ADDAR Address or Data register
0Fh RW RESERVED RESERVED
EXTENDED REGISTERS
10h RW PHYCR PHY Control Register
11h RO PHYSR PHY Status Register
12h RW MINTMR MII Interrupt Mask Register
13h RO MINTSR MII Interrupt Status Register
14h RW MINTCR MII Interrupt Control Register
15h RO RECR Receive Error Counter Register
16h RW BISCR BIST Control Register
17h RO BISSR BIST Status Register
18h RW LEDCR LED Direct Control Register
19h RW RESERVED RESERVED
1Ah RW CDCR Cable Diagnostic Control Register
1Bh RW CDSR Cable Diagnostic Status Register
1Ch RO CDRR Cable Diagnostic Results Register
1Dh-1Eh RW RESERVED RESERVED
1Fh RW PDR Power Down Register
42h RO FCSCR False Carrier Sense Counter Register
70h RW RXCCR RX Channel Control Register
71h RO BISBCR BIST Byte Count Register
72h RO BISECR BIST Error Count Register
7Bh RW BISPLR BIST Packet Length Register
7Ch RW BISIPGR BIST Inter Packet Gap Register
80h RW TDRSMR TDR State Machine Enable Register
90h RW TDRPAR TDR Pattern Amplitude Register
94h RW TDRMPR TDR Manual Pulse Register
0C00h–0C0Ch RW TDR Algorithm Registers
0C26h–0C2Ah RW ALCD/DSA Registers
0D00h, 0D01h, RAM registers
RW
0D04h
0107h RW CD Pre Test Configuration 1 Register
010Fh RW CD Pre Test Configuration 2 Register
00AC RW LPF Bypass Register
Copyright © 2009, Texas Instruments Incorporated Register Block 39
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