Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
determine if and how to cross. In some of the configurations, there may be situations in which the link is
not established. Particularly, it may occur if the TLK100 is forced to operate in 10B-T or 100B-TX modes
(auto-negotiation is disabled) and the other link partner activates auto-negotiation. For that reason, it is
recommended to disable the auto MDI/MDI-X function prior to disabling the auto-negotiation. However, the
user has the full ability to control the auto negotiation and the auto MDI/MDIX independently.
The cross-over mechanism can be turned off and forced to the MDI or MDI-X state by setting configuration
pin MDIX_EN (Pin 31), whose state is latched during power-up reset. When MDIX_EN is set to ‘0’, then
the crossover mechanism is disabled and the PHY operates in MDI or MDI/X mode respectively. If the pin
is set to '1', then the cross-over mechanism is enabled and MDI/MDI-X state is selected during operation.
The auto MDI/MDI-X crossover function is controlled by register PHYCR(0x10) bits [6:5]. MDI/MDI-X
status can be read through register PHYSR(0x11) bit 8.
5.5 Auto Negotiation
5.5.1 Operation
The auto negotiation function, described in detail in IEEE802.3 chapter 28, provides the means to
exchange information between two devices and automatically configure both of them to take maximum
advantage of their abilities. The auto negotiation uses the 10B-T link pulses. It encapsulates the
transmitted data in sequence of pulses, also referred to as a Fast Link Pulses (FLP) burst. The FLP Burst
consists of a series of closely spaced 10B-T link integrity test pulses that form an alternating clock/data
sequence. Extraction of the data bits from the FLP Burst yields a Link Code Word that identifies the
operational modes supported by the remote device, as well as some information used for the auto
negotiation function’s handshake mechanism.
The information exchanged between the devices during the auto-negotiation process consists of the
devices' abilities such as duplex support and speed. It allows higher levels of the network (MAC) to send
to the other link partner vendor-specific data (via the Next Page mechanism, see below), and provides the
mechanism for both parties to agree on the highest performance mode of operation.
When auto negotiation has started, the TLK100 transmits FLP on one twisted pair and listens on the other,
thus trying to find out whether the other link partner supports the auto negotiation function as well. The
decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates
auto negotiation, then the two parties begin to exchange their information. If the other link partner is a
legacy PHY or does not activate the auto negotiation, then the TLK100 uses the parallel detection
function, as described in IEEE802.3 chapters 40 and 28, to determine 10B-T or 100B-TX operation
modes. BMCR Register bit 6 reports whether the link was established using the auto negotiation or
parallel detection functions.
5.5.2 Initialization and Restart
The TLK100 initiates the auto negotiation function if it is enabled through the configuration jumper options
AN_EN, AN_1 and AN_0 (pins 34,35,36) and one of the following events has happened:
1. Hardware reset de-assertion.
2. Software reset (via register).
3. Auto negotiation restart (via register BMCR (0x0000h) bit 9).
4. Power-up sequence (via register BMCR (0x0000h) bit 11 ).
The auto-negotiation function is also initiated when the auto-negotiation enable bit is set in register BMCR
(0x0000h) bit 12 and one of the following events has happened:
1. Software restart.
2. Transitioning to link_fail state, as described in IEEE802.3.
32 Architecture Copyright © 2009, Texas Instruments Incorporated
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