Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
4.2 Serial Management Interface
The Serial Management Interface (SMI), provides access to the TLK100’s internal registers space for
status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The
implemented register set consists of all the registers required by the IEEE802.3-2002 in addition to several
others, providing additional visibility and controllability of the TLK100 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock
is sourced by the external management entity (also referred to as STA), and can run at maximum clock
rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management
entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is
latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (1.5kΩ) which,
during IDLE and turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used.
During power-up reset, the TLK100 latches the PHYAD[4:0] configuration pins (Pin 25 to Pin 28) to
determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset.
To maintain legal operation, SMI bus should remain inactive at least one MDC cycle after hard reset is
de-asserted.
In normal MDIO transactions, the register address is taken directly from the management frame’s
reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3
and vendor specific). The data field is used for both reading and writing.
The Start code is indicated by a <01> pattern. This makes sure that the MDIO line transitions from the
default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address
field and the Data field. To avoid contention during a read transaction, no device may actively drive the
MDIO signal during the first bit of Turnaround. The addressed TLK100 drives the MDIO with a zero for the
second bit of turnaround and follows this with the required data. Figure 4-2 shows the timing relationship
between MDC and the MDIO as driven/received by the Station (STA) and the TLK100 (PHY) for a typical
register read access.
22 Interfaces Copyright © 2009, Texas Instruments Incorporated
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