Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
MAC/
Switch
PCS
Signal
Process
PHY
AFE
PHY Digital
XFMR
&
RJ45
CAT5 Cable
LinkPartner
M
I
I
ReverseLoopback
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
3.5.2 Far-End Loopback
Far-end (Reverse) loopback is a special test mode to allow testing the PHY from link partner side. In this
mode data that is received from the link partner pass through the PHY's receiver, looped back on the MII
and transmitted back to the link partner. Figure 3-4 shows Far-end loopback functionality.
Figure 3-4. Block Diagram, Far-End Loopback Mode
The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII
register address 0x16.
While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface
and all data signals that come from the MAC are ignored.
3.6 BIST
The TLK100 incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit
testing or diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data
paths. The BIST testing can be performed using both internal loopback (digital or analog) or external loop
back using a cable fixture. The BIST simulates a real data transfer scenarios using real packets on the
lines. The BIST allows full control of the packets lengths and of the Inter Packet Gap (IPG)
The BIST is implemented with independent transmit and receive paths, with the transmit block generating
a continuous stream of a pseudo random sequence. The TLK100 generates a 23-bit pseudo random
sequence for doing the BIST test. The received data is compared to the generated pseudo-random data
by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of
error bytes that the PRBS checker received is stored in the BISECR register (0x72h).The number of
transmitted bytes that the PRBS checker received is stored in the BISBCR register (0x71h). The status of
whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS is in sync or
not and whether the packet generator is busy or not can be found by reading the BISSR register (0x17h).
The PRBS test can be put in a continuous mode or single mode by using the bit 15 of the BISCR register
(0x16h). In the continuous mode, when one of the PRBS counter reaches the maximum value the counter
starts counting from zero again. In the single mode when the PRBS counter reaches its maximum value
the PRBS checker stops counting.
TLK100 allows the user to control the length of the PRBS packet. By programming the BISPLR register
(0x7Bh) register one can set the length of the PRBS packet. There is also an option to generate a single
packet transmission of two types 64 and 1518 bytes through register bit – bit13 of the BISCR register
(0x16h). The single generated packet is composed of a constant data.
18 Configuration Copyright © 2009, Texas Instruments Incorporated
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