Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
LED_LINK
LED_SPEED
LED_ACT/COL
470 W 470 W470 W
2.2kW 2.2kW2.2kW
VCC
AN_EN=1 AN1=1 AN0=1
B0315-01
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
3.4 LED Interface
The TLK100 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED
configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes.
The LEDs can be controlled by configuration pin and/or internal register bits. Bits 6:5 of the LED Direct
Control register (LEDCR) selects the LED mode as described in Table 3-3.
Table 3-3. LED Mode Select
LED_CFG[1] LED_CFG[0]
Mode LED_LINK LED_SPEED LED_ACT
(bit 6) (bit 5) or (pin 22)
ON for Good Link ON in 100 Mb/s ON Pulse for Activity
1 don't care 1
OFF for No Link OFF in 10 Mb/s OFF for No Activity
ON for Good Link ON in 100 Mb/s None
2 0 0
BLINK for Activity OFF in 10 Mb/s
ON for Good Link ON in 100 Mb/s ON for Full Duplex
3 1 0
BLINK for Activity OFF in 10 Mb/s OFF for Half Duplex
The LED_LINK pin in Mode 1 indicates the link status of the port. It is OFF when no LINK is present. In
Mode 2 and Mode 3 it is ON to indicate Link is good and BLINK to indicate activity is present on either
transmit or receive channel. The blink rate is decided by the bits 9:8 of the LEDCR register (0x18). The
default blink rate is 5Hz.
The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. This LED is ON when the device is
operating in 100 Mb/s operation. The functionality of this LED is independent of mode selected.
The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED is ON
(Pulse) for Activity and OFF for No Activity. The width of the pulse is determined by the bits 14:13 of the
LEDCR register (0x18). The default pulse width is 200ms. In mode 3 this pin indicates the Duplex status
of operation. The LED is ON for Full Duplex and OFF for Half Duplex.
Bits 2:0 of the LEDCR register defines the polarity of the signals on the LED pins.
Since the Auto-Negotiation (AN) configuration options share the LED output pins, the external components
required for configuration-pin programming and those for LED usage must be considered in order to avoid
contention.
See Figure 3-2 for an example of AN connections to external components. In this example, the AN
programming results in Auto-Negotiation with 10/100 Half/Full-Duplex advertised.
Figure 3-2. AN Pin Configuration and LED Loading Example
16 Configuration Copyright © 2009, Texas Instruments Incorporated
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