Datasheet
Table Of Contents
- 1 Introduction
- Table of Contents
- 2 Pin Descriptions
- 3 Configuration
- 4 Interfaces
- 5 Architecture
- 6 Reset and Power Down Operation
- 7 Design Guidelines
- 8 Register Block
- 8.1 Register Definition
- 8.1.1 Basic Mode Control Register (BMCR)
- 8.1.2 Basic Mode Status Register (BMSR)
- 8.1.3 PHY Identifier Register #1 (PHYIDR1)
- 8.1.4 PHY Identifier Register #2 (PHYIDR2)
- 8.1.5 Auto-Negotiation Advertisement Register (ANAR)
- 8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
- 8.1.7 Auto-Negotiate Expansion Register (ANER)
- 8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)
- 8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
- 8.2 Register Control Register (REGCR)
- 8.3 Address or Data Register (ADDAR)
- 8.4 Extended Registers
- 8.4.1 PHY Control Register (PHYCR)
- 8.4.2 PHY Status Register (PHYSR)
- 8.4.3 MII Interrupt Mask Register (MINTMR)
- 8.4.4 MII Interrupt Status Register (MINTSR)
- 8.4.5 MII Interrupt Control Register (MINTCR)
- 8.4.6 Receiver Error Counter Register (RECR)
- 8.4.7 BIST Control Register (BISCR)
- 8.4.8 BIST STATUS Register (BISSR)
- 8.4.9 BIST Byte Count Register (BISBCR)
- 8.4.10 BIST Error Count Register (BISECR)
- 8.4.11 BIST Packet Length Register (BISPLR)
- 8.4.12 BIST Inter Packet Gap Register (BISIPGR)
- 8.4.13 LED Direct Control Register (LEDCR)
- 8.4.14 Power Down Register (PDR)
- 8.4.15 False Carrier Sense Counter Register (FCSCR)
- 8.4.16 RX Channel Control Register (RXCCR)
- 8.5 Cable Diagnostic Registers
- 8.5.1 Cable Diagnostic Registers (CDCR)
- 8.5.2 Cable Diagnostic Status Register (CDSR)
- 8.5.3 Cable Diagnostic Results Register (CDRR)
- 8.5.4 TDR State Machine Enable (TDRSMR)
- 8.5.5 TDR Pattern Amplitude Register (TDRPAR)
- 8.5.6 TDR Manual Pulse Register (TDRMPR)
- 8.5.7 TDR Channel Silence Register (TDRCSR)
- 8.5.8 TDR Control Register (TDRCR)
- 8.5.9 TDR Clock Cycles Register (TDRLCR)
- 8.5.10 TDR Low Threshold Register (TDRLT1)
- 8.5.11 TDR Low Threshold Register (TDRLT2)
- 8.5.12 TDR Low Threshold Register (TDRLT3)
- 8.5.13 TDR Low Threshold Register (TDRLT4)
- 8.5.14 TDR High Threshold Register (TDRHT1)
- 8.5.15 TDR High Threshold Register (TDRHT2)
- 8.5.16 TDR High Threshold Register (TDRHT3)
- 8.5.17 TDR High Threshold Register (TDRHT4)
- 8.5.18 TDR Pattern Control Register 1 (TDRLCR1)
- 8.5.19 TDR Pattern Control Register 2 (TDRLCR2)
- 8.5.20 DSA Configuration Register 1 (DSACR1)
- 8.5.21 DSA Configuration Register 2 (DSACR2)
- 8.5.22 DSA Start Frequency (DSASFR)
- 8.5.23 DSA Frequency Control (DSAFCR)
- 8.5.24 DSA Output Control (DSAOCR)
- 8.5.25 RAM Control 1 (RAMCR1)
- 8.5.26 RAM Control 2 (RAMCR2)
- 8.5.27 RAM Data Out (RAMDR)
- 8.5.28 CD Pre Test Configuration Control 1 (CDPTC1R)
- 8.5.29 CD Pre Test Configuration Control 2 (CDPTC2R)
- 8.5.30 LPF Bypass (LPFBR)
- 8.1 Register Definition
- 9 Electrical Specifications
- 10 Appendix A: Digital Spectrum Analyzer (DSA) Output
- Revision History
1 :1
1 :1
T1
RJ 45
3.3V
Supply
TLK100
11
VDD33_VA11
10
VA11_PFBOUT
1
VA11_PFBIN1
7
VA11_PFBIN2
21
VDD33_VD11
20
VDD11
.
17
VDD33_IO
29
VDD33_IO
5
RD–
RD–
6
RD+
RD+
49.9W
1.0 Fm
*
8
TD–
TD–
9
TD+
TD+
*
41
VDD33_V18
40
V18_PFBOUT
2
V18_PFBIN1
4
V18_PFBIN2
49.9W
49.9W
49.9W
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
3.3V
Supply
3.3V
Supply
0.1 Fm
1.0 Fm
1.0 Fm
3.3V
Supply
3.3V
Supply
TLK100
SLLS931B–AUGUST 2009–REVISED DECEMBER 2009
www.ti.com
2.10 Power Supply Configuration
The TLK100 provides best-in-class flexibility of power supplies.
• Single supply operation – If a single 3.3V power supply is desired, the TLK100 will sense the presence
of the supply and configure the internal voltage regulators to provide all necessary supply voltages. To
operate in this mode, connect the TLK100 supply pins according to the following scheme:
Figure 2-1. Power Scheme for Single Supply Operation
• Multiple Supply operation – When additional 1.8V and/or 1.1V external power rails are available, the
TLK100 can be configured in various ways as given in Table 2-1. This gives the highest flexibility for
the user and enables significant reduction in power consumption. When using multiple external
supplies, the internal regulators must be disabled by appropriate device connections.
– When an external 1.8V rail is available – Connect the external 1.8V to all following TLK100 pins to
enable proper operation: V18_PFBOUT (pin 40), V18_PFBIN1 (pin 2), V18_PFBIN2 (pin 4) and
VDD33_V18 (pin 41). In addition, connect the 1.8V rail to the transformer center tap to further
reduce the transmission power, as shown in Figure 2-2:
10 Pin Descriptions Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLK100