User's Guide SLLU168 – August 2012 TLK10034 Quad-Channel XAUI/10GBASE-KR Transceiver Evaluation Module (EVM) This user’s guide describes the usage and construction of the TLK10034 evaluation module (EVM). This document provides guidance on proper use by showing some device configurations and test modes. In addition, design, layout, and schematic information is provided. Use the information in this guide when choosing the optimal design methods and materials in designing a complete system.
www.ti.com WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
www.ti.com 19 TLK10034 EVM Schematic, Channel A High Speed Data Signals (Sheet 12 of 16) ............................. 28 20 TLK10034 EVM Schematic, Channel B High Speed Data Signals (Sheet 13 of 16) ............................. 29 21 TLK10034 EVM Schematic, Channel C & D High Speed Data Signals (Sheet 14 of 16) .......................
Introduction 1 www.ti.com 3 TLK10034 EVM Voltage Monitor Board Layer Construction......................................................... 69 4 TLK10034 EVM USB Dongle Board Layer Construction ............................................................. 76 Introduction The Texas Instruments (TI) TLK10034 SERDES evaluation module (EVM) boards evaluate the functionality and performance of the TLK10034 quad-channel, XAUI/10GBASE-KR transceiver device in a 324-pin PBGA package.
EVM PCB and High-Speed Design Considerations www.ti.com 2 EVM PCB and High-Speed Design Considerations Use the EVM for the evaluation of device parameters as well as a guide for high-speed board layout. As the frequency of operation increases, take special care to ensure that the highest signal integrity is maintained. This is achieved by controlling the board's impedance to 50-Ω single-ended or 100-Ω differential impedance for both the low- and high-speed differential serial and clock connections.
Power 4 www.ti.com Power The EVM motherboard is powered from one 5-V power supply and two 2p5-V power supplies. The 5-V power supply powers the board’s general logic IC’s, 1p5-, 1p8-, 2p5- and 3p3-V LDOs as well as the board’s LEDs. The 2p5-V analog and 2p5-V digital power supply inputs supply the four 1-V LDOs which source the various 1-V power rails for the core of the TLK10034 device.
Control and Output Status Signals www.ti.com 6 Control and Output Status Signals All of the external control and status pins on the EVM are consolidated to a single location on the board and broken out onto several header blocks and dip switches. LEDs are added to the LOSA, LOSB, LOSC, LOSD, LS_OK_OUT_A, LS_OK_OUT_B, LS_OK_OUT_C, LS_OK_OUT_D, and PRBS_PASS signals in addition to the headers for scope probes, to allow easy monitoring of the high/low value on the lines.
JTAG www.ti.com The USB Dongle implementing TI’s TUSB3210 microcontroller is the preferred method of controlling the TLK10034 register stack and is the only way to interface the GUI with the board. When the USB Dongle is connected to the EVM board through the Samtec MEC1 connector, the MDIO signals are at 3.3-V levels because the TUSB3210 is a 3.3-V device with open drain architecture. The EVM board has TI’s TXS0108EPWR bidirectional level shifter to convert the MDIO signals to the 1.
Test and Setup Configurations www.ti.com Depending upon the power down and or GUI-termination sequence followed, the USB device may need to be RESET to allow re-enumeration to occur in future tests. When the board is powered on and the USB connection is enumerated, the USB online LED (D4) lights on the USB Dongle board. If this LED fails to light, a PC-related issue may exist, and the PC must be restarted. The LED lights once the PC error is fixed.
Test and Setup Configurations www.ti.com Figure 1.
Test and Setup Configurations www.ti.com Figure 2.
Test and Setup Configurations www.ti.com Figure 3.
Test and Setup Configurations www.ti.com Figure 4.
Test and Setup Configurations www.ti.com Figure 5.
Test and Setup Configurations www.ti.com Figure 6.
Test and Setup Configurations www.ti.com Figure 7.
TLK10034 EVM Motherboard Schematics www.ti.com 11 TLK10034 EVM Motherboard Schematics 5 4 3 2 1 NOTES: 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS OTHER THAN SMP CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 3 INCHES OR LESS. 4. USE ROGERS MATERIAL FOR OUTSIDE LAYERS AND FR4-370 MATERIAL FOR INSIDE LAYERS. 5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.
TLK10034 EVM Motherboard Schematics www.ti.com 2 3 4 FB NC1 NC2 NC3 GND GND_PP MUST USE TPS74401 3A LDO 2 3 4 4.02K R7 88.7 C14 0.001uF TH2 MUST USE TPS74401 3A LDO R6 4.02K 1 3 5 7 ON 9 11 13 15 C 1P5V_REG_EN 1P8V_REG_EN 2P5V_REG_EN 3P3V_REG_EN 1P0V_A_REG2_TRIM C 1uF TH4 SW4 2 4 6 8 10 12 14 16 10uF 12 21 GND GND_PP TH3 C11 16 FB NC1 NC2 NC3 1.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 2.5V REGULATOR 1.5V REGULATOR 5V 5V 12 21 TPS74401RGW MUST USE TPS74401 3A LDO C41 0.001uF 2 2P5V_REG_EN FB 2 3 4 NC1 NC2 NC3 TPS74401RGW 2P5V_REG_TRIM 1P5V_REG_TRIM R24 10 3.3V REGULATOR U9 2 3 4 GND GND_PP 12 21 TPS74401RGW 2 3P3V_REG_EN SS FB NC1 NC2 NC3 GND GND_PP TPS74401RGW 10uF 9 13 14 17 B C51 NC4 NC5 NC6 68uF PG EN 3P3V 16 12 21 MUST USE TPS74401 3A LDO MUST USE TPS74401 3A LDO C55 0.001uF R30 C56 0.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 PLANE FILTERING / BULK DECOUPLING D D 1P8V 1P5V 5V 1P5/8V VDDA R34 0 R37 0 1uF 0.1uF C62 C63 C64 0.01uF 10uF C76 0.01uF 1uF 0.1uF C75 C74 1uF 0.1uF C91 C92 C93 0.01uF 10uF 0 C90 R43 C89 0.01uF 0 DVDD 1uF 0.1uF C108 C109 B C110 0.01uF 10uF 0.1uF C105 VDDD R40 1P0V_D2 C106 0.01uF 1uF C104 C61 10uF C73 C72 0.01uF 0.1uF C71 0.1uF C88 10uF C103 C 1P0V_D1 VDDRD_LS VDDRD_HS 0.1uF C122 C123 0.
TLK10034 EVM Motherboard Schematics www.ti.
TLK10034 EVM Motherboard Schematics www.ti.com 4 3 2 1 TLK10034 DEVICE POWER / LOCAL DECOUPLING VDDO NOTE: PLACE CAPACITORS VDDO DECOUPLLING GENERAL GUIDELINES: 1. PLACE CAPACITORS SUCH THAT SMALLER VALUE CAPACITORS ARE NEARER THE DUT AND THEN SUCCESSIVELY PLACE LARGER VALUE CAPACITORS AS YOU MOVE AWAY FROM THE DUT. NEAR TLK10034 DEVICE 0.1uF 0.1uF 0.1uF C129 C131 D 0.1uF 1P5_8V_VDDO0 1P5_8V_VDDO1 1P5_8V_VDDO2 1P5_8V_VDDO3 2. PLACE CAPACITORS NEAR VIAS AND CONNECTORS.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 VDDO 3P3V 2 1 VDDO 5V 3P3V 3P3V R61 R82 BI-DIRECTIONAL I/0 PINS U17B 9 10 11 12 13 14 15 16 TCA6424 TXB0108PWR I2C_DIS_FET CHA/B_MDIO_RELAY CHC/D_MDIO_RELAY R110 R111 JMP27 2 4 1 3 FDV301N 5 FDV301N 4 130 B Header 2x2 5V GPI2 AMUXA_HS AMUXB_LS GP2_G AMUXB_HS AMUXC_LS AMUXC_HS AMUXD_LS AMUXD_HS FDV301N Q2 Q3 G S G FDV301N 49.9K 49.9K 49.9K DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.99K DNI_4.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 K4 3 15 15 MDIO_LS K3 ROUTE THE MDIO/MDC 4 VDDO SIGNALS THROUGH THE PADS OVERLAP RESISTOR PADS OF R264 AND OF THE RELAYS TO MINIMIZE PRTAD3 PRTAD2 PRTAD1 2 4 6 8 2 EXT_I2C_SDA EXT_I2C_RESET1 EXT_I2C_INT1 EXT_I2C_RESET2 EXT_I2C_INT2 Header 2x6 I2C BUS CONNECTOR R195 I2C_GPIO_ADDR 26 VCCP VCCI SCL SDA ADDR RESET 25 33 3P3V 3P3V GND PP INT 31 DNI_4.99K DNI_4.99K BUS.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 NOTE: C196 0.1uF HSRXA_CLKOUTP 1 J8 HSRXA_CLKOUTP HSRXA_CLKOUTP_SMP 1. MATCH REFCLK0/1_P/N AND CLKOUT0/1_P/N TRACE LENGTHS TO EACHOTHER SMA SURFACE C197 0.1uF HSRXA_CLKOUTN J9 HSRXA_CLKOUTN HSRXA_CLKOUTN_SMP SMA SURFACE D C198 D 0.1uF HSRXB_CLKOUTP C199 HSRXB_CLKOUTP_CONNECTOR 15 HSRXB_CLKOUTN_CONNECTOR 15 0.1uF HSRXB_CLKOUTN C200 0.1uF HSRXC_CLKOUTP C201 HSRXC_CLKOUTP_CONNECTOR 16 HSRXC_CLKOUTN_CONNECTOR 16 0.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTE: 1. MATCH LOW SPEED INPUT AND OUTPUT TRACE LENGTHS TO EACHOTHER 2. MATCH HIGH SPEED TRANSMIT AND RECEIVE TRACE LENGTHS TO EACHOTHER INA0P INA0P_CONNECTOR C216 0.1uF C218 0.1uF INA0N INA0N_CONNECTOR 15 15 15 15 INB0P INB0P_CONNECTOR C217 0.1uF C219 0.1uF INB0N INB0N_CONNECTOR D D INA1P C220 INB1P INA1P_CONNECTOR 15 15 INB1P_CONNECTOR INA1N_CONNECTOR 15 15 INB1N_CONNECTOR 0.1uF INA1N C222 0.1uF C224 0.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 NOTE: 1. MATCH LOW SPEED INPUT AND OUTPUT TRACE LENGTHS TO EACHOTHER 2. MATCH HIGH SPEED TRANSMIT AND RECEIVE TRACE LENGTHS TO EACHOTHER INC0P INC0P_CONNECTOR C232 0.1uF C234 0.1uF INC0N INC0N_CONNECTOR 16 16 16 16 IND0P IND0P_CONNECTOR C233 0.1uF C235 0.1uF IND0N IND0N_CONNECTOR D D INC1P C236 IND1P INC1P_CONNECTOR 16 16 IND1P_CONNECTOR INC1N_CONNECTOR 16 16 IND1N_CONNECTOR 0.1uF INC1N C238 0.1uF C240 0.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 3P3V J25B 100 D15 E1 3P3V_TXA RX_LOS 3P3V CHA_MOD_DEF2_SDA CHA_MOD_DEF1_SCL 4 5 4.99K 4.99K 6 VEET1 VEET2 VEET3 MOD-DEF0_ABS VEER1 VEER2 VEER3 RATE_SEL_0 RATE_SEL_1 JMP37 B 2 4 2 RED ZXTD09N50DE6 3 U22 8 R259 C1 44.2K 6 1 17 20 R262 CHA_TX_FAULT 10 11 14 C2 44.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 3P3V J26B 4.7uH 100 D20 E1 3P3V_TXB RX_LOS 3P3V CHB_MOD_DEF2_SDA CHB_MOD_DEF1_SCL 4 5 4.99K 4.99K 6 RED ZXTD09N50DE6 3 U25 8 R282 C1 44.2K 6 VEET1 VEET2 VEET3 MOD-DEF0_ABS VEER1 VEER2 VEER3 RATE_SEL_0 RATE_SEL_1 1 17 20 R285 CHB_TX_FAULT 10 11 14 CHB_RX_LOS C2 44.
TLK10034 EVM Motherboard Schematics www.ti.com 5 4 3 2 1 D D HSTXCP_SMA J20 HSTXDP J16 HSTXCP EDGE LAUNCH R290 U1C C HSTXCP HSTXCN A14 A15 HSRXCP HSRXCN 0 R291 HSTXCP HSTXCN HSTXCN_SMA J17 HSTXCN J21 HSTXDN EDGE LAUNCH R292 A12 A11 HSRXCP_SMA J18 HSRXCP J22 HSRXDP EDGE LAUNCH HSRXCN_SMA J19 HSRXCN J23 HSRXDN EDGE LAUNCH C264 HSTXDN V11 V10 C HSTXDP HSTXDN 0 HSRXDP_SMA HSRXDP HSRXDN EDGE LAUNCH 0.
TLK10034 EVM Motherboard Schematics www.ti.
TLK10034 EVM Motherboard Schematics www.ti.
TLK10034 EVM Motherboard Layout www.ti.com 12 TLK10034 EVM Motherboard Layout Figure 24.
TLK10034 EVM Motherboard Layout www.ti.com Figure 25.
TLK10034 EVM Motherboard Layout www.ti.com Figure 26.
TLK10034 EVM Motherboard Layout www.ti.com Figure 27.
TLK10034 EVM Motherboard Layout www.ti.com Figure 28.
TLK10034 EVM Motherboard Layout www.ti.com Figure 29.
TLK10034 EVM Motherboard Layout www.ti.com Figure 30.
TLK10034 EVM Motherboard Layout www.ti.com Figure 31.
TLK10034 EVM Motherboard Layout www.ti.com Figure 32.
TLK10034 EVM Motherboard Layout www.ti.com Figure 33.
TLK10034 EVM Motherboard Layout www.ti.com Figure 34.
TLK10034 EVM Motherboard Layout www.ti.com Figure 35.
TLK10034 EVM Motherboard Layout www.ti.com Table 1.
TLK10034 EVM SMA Breakout Board Schematics 13 www.ti.com TLK10034 EVM SMA Breakout Board Schematics 5 4 3 2 1 NOTES: 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS OTHER THAN SMA CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS 100 OHM DIFFERENTIALLY COUPLED OR SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 5 INCHES OR LESS. ALL OTHER DATA LINES SHOULD BE 50 OHM IMPEDIANCE ON INTERNAL OR EXTERNAL LAYERS.
TLK10034 EVM SMA Breakout Board Schematics www.ti.
TLK10034 EVM SMA Breakout Board Schematics www.ti.
TLK10034 EVM SMA Breakout Board Schematics www.ti.
TLK10034 EVM SMA Breakout Board Layout 14 www.ti.com TLK10034 EVM SMA Breakout Board Layout Figure 40.
TLK10034 EVM SMA Breakout Board Layout www.ti.com Figure 41.
TLK10034 EVM SMA Breakout Board Layout www.ti.com Figure 42.
TLK10034 EVM SMA Breakout Board Layout www.ti.com Figure 43.
TLK10034 EVM SMA Breakout Board Layout www.ti.com Table 2. TLK10034 EVM SMA Breakout Board Layer Construction Subclass Name TOP L2_GND L3_GND L4_GND BOTTOM Thickness (MIL) Dielectric Constant Type Material SURFACE AIR CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER DIELECTRIC PLANE DIELECTRIC FR-4 PLANE COPPER 1.2 1 DIELECTRIC FR-4 20 4.5 CONDUCTOR COPPER 2 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 1 2 1 5 4.5 1.2 1 FR-4 20 4.5 COPPER 1.2 1 4 4.
TLK10034 EVM Voltage-Monitor Board Schematics www.ti.com 15 TLK10034 EVM Voltage-Monitor Board Schematics 5 4 3 2 1 NOTES: 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS ON A 0 OR 90 DEGREE ORIENTATION. 3. VOLTAGE SENSE LINES SHOULD BE ROUTED AS WIDE AS POSSIBLE TO REDUCE IR DROP. 4. USE FR4-370 MATERIAL FOR ALL LAYERS. 5. PLACE TI LOGO IN TOP SIDE METAL D D 6. PCB MUST BE 0.062 INCHES THICK 7.
TLK10034 EVM Voltage-Monitor Board Schematics 5 www.ti.com 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 5V 4P096V_REF1 5V 4P096V_REF2 5V 5V U1 R4 LM339A VCC GND 12 4P096V_REF2 4 5V LM339A 3 IN_P + - 3 OUT 14 R14 3 IN_N R17 3.48K U2E 1P0V_D1_B 8 2 IN_N + - 2 OUT 9.
TLK10034 EVM Voltage-Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE.
TLK10034 EVM Voltage-Monitor Board Schematics 5 www.ti.com 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. D D 4P096V_REF5 5V 5V 4P096V_REF6 5V 5V U13 LM339A VCC GND U15 4 5V LM339A 14 VDDT_B 3 IN_N 3 OUT R58 3.48K U14E 9.76K VDDT_0P85V_VREF 10 4 IN_P 4 IN_N + - 2 OUT 4 OUT U18 C1 5 U17D R56 ZXTD09N50DE6 9 8 LM339A DVDD E2 3 IN_P 3 IN_N + - 3 OUT 14 R59 3.
TLK10034 EVM Voltage-Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE.
TLK10034 EVM Voltage-Monitor Board Schematics 5 www.ti.com 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE.
TLK10034 EVM Voltage-Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE.
TLK10034 EVM Voltage-Monitor Board Schematics 5 www.ti.com 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR C RCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE.
TLK10034 EVM Voltage-Monitor Board Schematics www.ti.com 5 4 3 2 1 NOTE: VOLTAGE WINDOW DETECTOR CIRCUITS MONITOR THE VOLTAGE ON THE PLANE AND LIGHTS THE APPROPRIATE LED IF IT IS WITHIN THE ALLOWABLE DATASHEET RANGE. IF THIS BOARD IS USED ON THE LAB CHARACTERIZATION BENCH BOARD, THE VDDA AND VDDT PLANES ARE SPLIT TO SEPERAT LOW SPEED AND HIGH SPEED PLANES. THE HIGH SPEED PLANES ARE MONITORED ON THIS BOARD AND THE LOW SPEED PLANES ARE MONITORED DIRECTLY ON THE BENCH BOARD.
TLK10034 EVM Voltage-Monitor Board Schematics 5 www.ti.
TLK10034 EVM Voltage Monitor Board Layout www.ti.com 16 TLK10034 EVM Voltage Monitor Board Layout Figure 54.
TLK10034 EVM Voltage Monitor Board Layout www.ti.com Figure 55.
TLK10034 EVM Voltage Monitor Board Layout www.ti.com Figure 56.
TLK10034 EVM Voltage Monitor Board Layout www.ti.com Figure 57.
TLK10034 EVM Voltage Monitor Board Layout www.ti.com Table 3. TLK10034 EVM Voltage Monitor Board Layer Construction Subclass Name TOP L2_GND L3_PWR BOTTOM Thickness (MIL) Dielectric Constant Type Material SURFACE AIR CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER 1.2 1 DIELECTRIC FR-4 45 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.5 CONDUCTOR COPPER 2 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 8.5 (Single) None/None (Single) 8.
TLK10034 EVM USB Dongle Board Schematics 17 www.ti.com TLK10034 EVM USB Dongle Board Schematics 5 4 3 2 1 NOTES: 1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS. 2. PLACE ALL PARTS ON A 0 OR 90 DEGREE ORIENTATION. 3. SERIAL DATA SHOULD BE ROUTED AS SINGLE-ENDED 50 OHM TRANSMISSION LINES ON OUTSIDE LAYERS. 4. USE FR4-370 MATERIAL FOR ALL LAYERS. 5. PCB MUST BE 0.062 IN THICK D D 6.
TLK10034 EVM USB Dongle Board Schematics www.ti.com 3 17 18 19 PUR DP R15 R16 DM_CON DP_CON 33 33 DM C15 22pF TUSB3210 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 1 1M 61 60 X1 USB Type B-mini Conn X1 X2 22pF 38 8 9 S2 4.99K R98 4.99K 4.99K R96 R105 R106 R107 R97 DNI_4.99K 1.5K 1.5K EEPROM 24LC512-I/SM EE_SCL 12 11 EE_SCL_S EE_SDA P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 /VREN S2 S3 GND1 GND2 GND3 GND4 GND5 USB PROGRAMMING SWITCH SW2 1 PIN DIP SMD 1 2 WP 52.3K 0.
TLK10034 EVM USB Dongle Board Layout 18 www.ti.com TLK10034 EVM USB Dongle Board Layout Figure 60.
TLK10034 EVM USB Dongle Board Layout www.ti.com Figure 61.
TLK10034 EVM USB Dongle Board Layout www.ti.com Figure 62.
TLK10034 EVM USB Dongle Board Layout www.ti.com Figure 63.
TLK10034 EVM USB Dongle Board Layout www.ti.com Table 4. TLK10034 EVM USB Dongle Board Layer Construction Subclass Name Type TOP L2_GND L3_PWR BOTTOM Material Thickness (MIL) Dielectric Constant SURFACE AIR CONDUCTOR COPPER DIELECTRIC FR-4 PLANE COPPER 1.2 1 DIELECTRIC FR-4 45 4.5 PLANE COPPER 1.2 1 DIELECTRIC FR-4 5 4.5 CONDUCTOR COPPER 2 1 SURFACE AIR Width (MIL) Coupling Type / Spacing (MIL) 8.5 (Single) None/None (Single) 8.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
