Datasheet

TLK10002EVM FPGA Daughterboard Layout www.ti.com
Table 4. TLK10002EVM FPGA Daughterboard Layer Construction
SUBCLASS THICKNESS DIELECTRIC LOSS WIDTH COUPLING TYPE/SPACING IMPEDANCE
(1)
TYPE MATERIAL
NAME (MIL) CONSTANT TANGENT (MIL) (MIL) (Ω)
SURFACE AIR 1 0
TOP CONDUCTOR COPPER 1.96 4.1 0 6.00 Edge/5.00 97.298
DIELECTRIC FR-4 5 4.1 0.035
L2_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L3_SIG2 CONDUCTOR COPPER 1.2 1 0 5.00 NONE/NONE 49.7
DIELECTRIC FR-4 10 4.1 0.035
L4_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L5_PWR CONDUCTOR COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L6_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L7_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 10 4.1 0.035
L8_PWR PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L9_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L10_PWR PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
L11_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 10 4.1 0.035
L12_SIG3 CONDUCTOR COPPER 1.2 1 0 5.0 NONE/NONE 49.7
DIELECTRIC FR-4 5 4.1 0.035
L13_GND PLANE COPPER 1.2 1 0
DIELECTRIC FR-4 5 4.1 0.035
BOTTOM CONDUCTOR COPPER 1.96 1 0 9.50 NONE/NONE 48.425
SURFACE AIR
(1)
The Impedance is set to be slightly less than 50 Ω or 100 Ω on the traces in order to compensate for slight over-etching during the manufacturing process. The end impedance after
etching should result in a 50 or 100-Ω Impedance. Always consult with your board manufacturer for their process/design requirements to ensure the desired impedance is achieved.
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TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module SLLU148– May 2011
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