Datasheet

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7 JTAG
The EVM also provides a separate connector to support the full five-pin JTAG interface of the TLK10002
with onboard level shifters to be compatible with most standard JTAG control interfaces to be used for
manufacturing tests. The 3.3-V (header) side of the level shifter is connected to the header and the
1p5/8V side of the level shifter is connected to the TLK10002. If the level shifter is not needed, providing
an external voltage of the appropriate signal level between pins 2 and 3 of JMP62 allows the signals to
pass to the TLK10002 correctly.
8 Reset
The TLK10002EVM comes configured for manual reset operations involving the pushbutton reset switch
(SW3). When switch SW3 is pressed, the TLK10002 device RESET pin (RST_N) goes LOW, and the
entire TLK10002 device is reinitialized. A TI TPS3125J18 ultralow-voltage processor supervisory circuit is
used to control the reset line. During power-on, RESET pin of U37 is asserted when the supply voltage
becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors the voltage and keeps
RESET output active as long as the voltage remains below the threshold voltage (V
IT
). An internal timer
delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, t
d
= 180 ms, starts after the voltage has risen above the threshold voltage (V
IT
).
A manual reset input to the supervisory circuit, MR, accepts the input from the pushbutton switch SW3. A
low level at MR causes RESET to become active, thus resetting the TLK10002 device whenever the
pushbutton RESET is pressed. By placing a jumper on JMP43, the manual reset (/MR) is tied hard to
ground causing the TLK10002 to be held in a constant state of reset without the need to continually hold
the Reset Pushbutton SW3. The supervisory circuit releases the reset line to a HIGH 180 ms (t
d
) from the
time the MR line becomes greater than the threshold voltage (V
IT
).
By removing the jumper from JMP42, the supervised reset circuit is disconnected from the RST_N line.
Reset control from an external controller or piece of equipment can be connected directly to pin 2
(RST_N) of JMP42 and a ground pin GND has been added to the JMP42 header next to the RST_N pin
to allow easy access for the return current on that cable.
The CDCE72010 jitter cleaner RESET signal is also connected to the Main Reset pushbutton as well as
individually controlled by pressing SW4. Note this RESET does not reset the CDCE72010 register stack
settings and is only a PLL reset.
NOTE: In order to keep the GUI settings and the device settings synchronized during the evaluation
of the TLK10002, all RESET commands must be issued through the GUI via the TCA6424
I2C-to-GPIO device connected to the signals. When the software RESET buttons are
pressed, the GUI adjusts its memory settings of the various registers in order to match the
new values the devices will reflect after the hardware RESET is performed. If the buttons are
pressed on the board, the GUI does not reflect the devices' true status and may result in
erroneous results during testing because the device is not configured according to the GUI’s
displayed results.
8
TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module SLLU148– May 2011
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