Datasheet
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
B
NA
6522851
FPGA USER PROGRAMMABLE RESOURCES
9 15
REV
PAGE
DOCUMENT NUMBER
SIZE
of
PAGE TITLE
TEXAS INSTRUMENTS
Q11
FDV301N
G
S
D
D10 ORANGE
2
1
R260 4.99K
R243
0
Q7
FDV301N
G
S
D
R250 4.99K
R259 4.99K
Q4
FDV301N
G
S
D
Q1
FDV301N
G
S
D
6SLX75TFGG676
U1I
IO_L43N_GCLK22_IRDY2_M3CASN_3
R6
IO_L51P_M3A10_3
N8
IO_L51N_M3A4_3
N7
IO_L52P_M3A8_3
R4
IO_L52N_M3A9_3
R3
IO_L10P_3
U4
IO_L53N_M3A12_3
P8
IO_L54P_M3RESET_3
N5
IO_L54N_M3A11_3
N4
IO_L10N_3
U3
IO_L55N_M3A14_3
N9
IO_L57P_3
M10
IO_L58P_4
M4
IO_L59P_M4DQ14_4
N2
IO_L59N_M4DQ15_4
N1
IO_L60P_M4DQ12_4
M3
IO_L60N_M4DQ13_4
M1
IO_L61P_M4UDQS_4
L2
IO_L61N_M4UDQSN_4
L1
IO_L62P_M4DQ10_4
K3
IO_L62N_M4DQ11_4
K1
R220 250
JMP22
Header 2x20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R262 4.99K
R242 250
R228 250
D12 RED
2
1
R251 4.99K
R261 4.99K
R240 250
R225
0
6SLX75TFGG676
U1H
IO_L24P_0
B5
IO_L32P_0
J11
IO_L6P_M5A10_5
F22
IO_L7P_M5WE_5
J20
IO_L4P_2
W20
IO_L16P_2
Y17
IO_L33P_M3DQ12_3
AD3
IO_L34P_M3UDQS_3
AC2
IO_L70P_M4RASN_4
L9
IO_L49P_M1DQ10_1
AB24
IO_L50P_M1UDQS_1
AC25
IO_L71P_M4A5_4
L4
R231
0
R237 0
R263 4.99K
R223
0
Q2
FDV301N
G
S
D
R244 4.99K
R252 4.99K
Q12
FDV301N
G
S
D
R233
0
R238 250
R235
0
R226 250
R253 4.99K
6SLX75TFGG676
U1J
IO_L35P_GCLK17_0
C13
IO_L36N_GCLK14_0
A12
IO_L37N_GCLK12_0
A14
IO_L41P_GCLK27_M3DQ4_3
T3
IO_L42P_GCLK25_TRDY2_M3UDM_3
V4
R246 4.99K
J11
GCLK25
SMA SURFACE
Q8
FDV301N
G
S
D
Q3
FDV301N
G
S
D
J10
GCLK27
SMA SURFACE
R245 4.99K
R234 250
J9
GCLK12
SMA SURFACE
R236 250
R224 250
R267
0
D4 RED
2
1
D8 RED
2
1
R254 4.99K
R266
0
Q9
FDV301N
G
S
D
R248 4.99K
R255 4.99K
R232 250
Q5
FDV301N
G
S
D
D3 GREEN
2
1
R265
0
D7 GREEN
2
1
J8
GCLK14
SMA SURFACE
R219
0
Q10
FDV301N
G
S
D
R247 4.99K
D2 ORANGE
2
1
D6 ORANGE
2
1
R256 4.99K
R239
0
R264
0
J7
GCLK17
SMA SURFACE
R221 0
R229 0
R257 4.99K
Q6
FDV301N
G
S
D
D1 YELLOW
2
1
D5 YELLOW
2
1
R222 250
JMP23 2 Pin Berg
1
2
D11 GREEN
2
1
R249 4.99K
R227
0
R258 4.99K
R230 250
D9 YELLOW
2
1
R241
0
IO_SIGNALS_28
IO_SIGNALS_24
IO_SIGNALS_36
IO_SIGNALS_32
IO_SIGNALS_CLK 2
IO_SIGNALS_38
IO_SIGNALS_34
IO_SIGNALS_26
IO_SIGNALS_30
IO_SIGNALS_20
IO_SIGNALS_22
IO_SIGNALS_23
IO_SIGNALS_25
IO_SIGNALS_27
IO_SIGNALS_29
IO_SIGNALS_31
IO_SIGNALS_21
IO_SIGNALS_33
IO_SIGNALS_35
IO_SIGNALS_37
IO_SIGNALS_39
GCLK17_SMA
GCLK14_SMA
GCLK12_SMA
GCLK27_SMA
GCLK25_SMA
GCLK25
GCLK27
GCLK12
GCLK14
GCLK17
LED9_G
LED9_L
LED9_D
LED12_G
LED11_G
LED12_L
LED12_D
LED10_G
LED10_L
LED10_D
LED11_L
LED11_D
LED5_G
LED5_L
LED5_D
LED8_G
LED7_G
LED8_L
LED8_D
LED6_G
LED6_L
LED6_D
LED7_L
LED7_D
LED12
LED11
LED10
LED9
LED8
LED7
LED6
LED5
LED1_G
LED1_L
LED1_D
LED4_G
LED3_G
LED4_L
LED4_D
LED2_G
LED2_L
LED2_D
LED3_L
LED3_D
LED4
LED3
LED2
LED1
VCCO_1P8V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
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TLK10002EVM FPGA Daughterboard Schematics
Figure 47. User Programmable Resources 1, Sheet 9 of 15
61
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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