Datasheet
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
B
NA
6522851
FPGA TI PROGRAMMED RESOURCES
7 15
REV
PAGE
DOCUMENT NUMBER
SIZE
of
PAGE TITLE
TEXAS INSTRUMENTS
R131 130
R181
0
R149 20K
D25 ORANGE
2
1
R153 4.99K
R140 4.99K
JMP16 2 Pin Berg
1
2
Q30
FDV301N
G
S
D
R169 4.99K
Q24
FDV301N
G
S
D
JMP14
Header 5x2
1
3
5
7
9
2
4
6
8
10
R159 4.99K
D30 GREEN
2
1
R132 10K
R147 4.99K
R167 4.99K
R174 250
R142 4.99K
R155 4.99K
R164 4.99K
R177 250
R184
0
R137 4.99K
R162 4.99K
R183 0
R173 250
R130
4.99K
R158 4.99K
D24 YELLOW
2
1
D26 YELLOW
2
1
U16
TPS3125J18
/RST
1
GND
2
RST
3
VDD
5
/MR
4
R161 4.99K
R144 4.99K
R186 0
R135 100K
R171 250
R139 4.99K
U17
ZXTD09N50DE6
C1
1
E1
2
C2
3
B2
4
E2
5
B1
6
D28 RED
2
1
R175 250
R152 4.99K
JMP15
Header 4x2
1
3
5
7
2
4
6
8
JMP17
Header 2x20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D27 ORANGE
2
1
Q28
FDV301N
G
S
D
R146 4.99K
Q23
FDV301N
G
S
D
R170 4.99K
R178 250
R179
0
R160 4.99K
R141 4.99K
R157 4.99K
R168 4.99K
R136 4.99K
R166 4.99K
D22 RED
2
1
D29 RED
2
1
R154 4.99K
R165 4.99K
R148 4.99K
R180 0
R182
0
Q26
FDV301N
G
S
D
6SLX75TFGG676
U1L
IO_L32N_GCLK28_2
AF14
IO_L41P_2
Y11
IO_L46P_2
V11
IO_L46N_2
V10
IO_L47P_2
AA9
IO_L47N_2
AB9
IO_L61P_2
AC5
IO_L63P_2
AD4
IO_L63N_2
AF4
IO_L2P_3
AA4
IO_L2N_3
AA3
IO_L7P_3
Y6
IO_L7N_3
Y5
IO_L8P_3
AB4
IO_L8N_3
AC3
IO_L9P_3
V7
IO_L9N_3
V6
IO_L53P_M3CKE_3
R9
IO_L55P_M3A13_3
P10
IO_L18P_3
U9
IO_L18N_3
U8
R150 20K
R163 4.99K
R143 4.99K
R138 4.99K
R176 250
D23 GREEN
2
1
6SLX75TFGG676
U1G
IO_L2P_0
H8
IO_L22P_0
B4
IO_L3P_0
F7
IO_L13P_0
H9
IO_L14P_0
A3
IO_L28P_2
AA15
IO_L28N_2
AB15
IO_L17P_2
U15
IO_L17N_2
V16
IO_L15P_2
AA21
IO_L15N_2
AB21
IO_L68P_1
U19
IO_L68N_1
U20
IO_L58P_0
H17
IO_L59P_0
C21
IO_L67P_1
AA23
IO_L66P_1
T19
IO_L5P_2
AB22
IO_L5N_2
AC22
IO_L33P_2
Y12
IO_L33N_2
AA12
IO_L34N_2
Y13
JMP12
2 Pin Berg
1
2
R133 49.9
R185
0
R156 4.99K
Q29
FDV301N
G
S
D
R134 130
Q25
FDV301N
G
S
D
R151 4.99K
C233
0.1uF
R172 250
R145 4.99K
D31 GREEN
2
1
Q27
FDV301N
G
S
D
JMP13
Header 8x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SW8
Light Touch Switch
1
2
5
4
3
RESET_N_(IO_L2P _0)
MAIN_RST_B
MAIN_RST_L
MAIN_/RST_L
MAIN_RST_C
MAIN_/RST_C
MAIN_/RST_B
MAIN_/RST
MAIN_RST
MAIN_RST_SIGN AL
PDTRXA_N
PRBSEN
TEST_EN_A
TEST_EN_B
LANE2_4_SELECT_A
LANE2_4_SELECT_B
LOOPBACK_A
LOOPBACK_B
GPIO_1_(IO_L5P _2)
GPIO_2_(IO_L5N_2 )
GPIO_3_(IO_L33P_ 2)
GPIO_4_(IO_L33N _2)
GPIO_5_(IO_L34N _2)
LS_OK_IN_A_G
LS_OK_OUT_A_G
LS_OK_IN_A_L
LS_OK_IN_A_D
LS_OK_IN_B_G
LS_OK_IN_B_L
LS_OK_IN_B_D
LS_OK_OUT_A_L
LS_OK_OUT_A_D
LS_OK_OUT_B_G
LOSA_G
LS_OK_OUT_B_L
LS_OK_OUT_B_D
LOSB_G
LOSB_L
LOSB_D
LOSA_L
LOSA_D
TEST_PAS S_A_G
TEST_PAS S_B_G
TEST_PAS S_A_L
TEST_PAS S_A_D
TEST_PAS S_B_L
TEST_PAS S_B_D
LOSA_(IO_L13P_0 )
LOSB_(IO_L14P_0 )
TEST_PASS_A_( IO_L68P_1)
TEST_PASS_B_( IO_L68N_1)
IO_SIGNALS_0
IO_SIGNALS_2
IO_SIGNALS_3
IO_SIGNALS_5
IO_SIGNALS_7
IO_SIGNALS_9
IO_SIGNALS_11
IO_SIGNALS_13
IO_SIGNALS_15
IO_SIGNALS_17
IO_SIGNALS_19
IO_SIGNALS_8
IO_SIGNALS_4
IO_SIGNALS_16
IO_SIGNALS_12
IO_SIGNALS_18
IO_SIGNALS_14
IO_SIGNALS_6
IO_SIGNALS_10
IO_SIGNALS_CLK 1
IO_SIGNALS_1
VCCO_1P8V
VCCO_1P8V
5V
5V
VCCO_1P8V
5V
5V
5V
5V
5V
5V
5V
5V
VCCO_1P8V
VCCO_1P8V
LS_OK_IN_A_CONNECTOR
12
LS_OK_IN_B_CONNECTOR
12
LS_OK_OUT_A_CONNECTOR
12
LS_OK_OUT_B_CONNECTOR
12
VOLTAGE SUPERVISOR
AND RESET MONITOR
MAIN RESET
PUSHBUTTON
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TLK10002EVM FPGA Daughterboard Schematics
Figure 45. TI-Programmed Resources 1, Sheet 7 of 15
59
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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