Datasheet
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
6522851
J. NERGER
J. NERGER
J. NERGER
TLK10002 EVM
SPARTAN-6 FPGA DAUGHTER BOARD
11/15/10
11/15/10
11/15/10
B
NA
COVER SHEET AND NOTES
1 15
SIZE
DOCUMENT NUMBER
REV SHEET
of
ENGINEER
LAYOUT
RELEASED
DATE
DATE
DATE
SCHEMATIC TITLE
TEXAS INSTRUMENTS
PAGE TITLE
-------
xx/xx/xx
REVISIONS
ECR
ECR NUMBER
DATE
NOTES:
1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS.
2. PLACE ALL PARTS OTHER THAN SMA CONNECTORS ON A 0 OR 90 DEGREE
ORIENTATION.
3. SERIAL DATA SHOULD BE ROUTED AS 100 OHM DIFFERENTIALLY COU
PLED OR SINGLE-ENDED 50 OHM TRANSMISSION LINES ON
OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 5 INCHES OR LESS.
ALL OTHER DATA LINES SHOULD BE 50 OHM IMPEDIANCE ON
INTERNAL OR EXTERNAL LAYERS. ROUTED POWER SHOULD BE A MINIMU
M OF 40 MILS WIDE.
4. USE ROGERS MATERIAL FOR OUTSIDE LAYERS AND FR4-370 MATERI
AL FOR INSIDE LAYERS.
5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.5 MILS
6. MATCH DIFFERENTIAL TRACE WIDTHS OF SERIAL AND REFCLK LINE
S WITH SMP/SMA PADS.
7. PLACE TI LOGO, BOARD NAME, JN COMBO LOGO, AND THE BOARD NUMB
ER IN TOP SIDE METAL.
TLK10002 DATA SHEET REVISION: 0.7
DATA SHEET LAST UPDATED ON: 09/27/10
SCHEMATIC SHEET INDEX:
SHEET 01: SPARTAN-6 BOARD COVER SHEET AND NOTES
SHEET 02: USB INTERFACE
SHEET 03: REGULATORS
SHEET 04: FPGA POWER AND GROUND
SHEET 05: FPGA CONFIGURATION
SHEET 06: FPGA MULTI-GIGABIT TRANSCEIVERS
SHEET 07: TI PROGRAMMED RESOURCES 1
SHEET 08: TI PROGRAMMED RESOURCES 2
SHEET 09: FPGA USER PROGRAMMABLE RESOURCES 1
SHEET 10: FPGA USER PROGRAMMABLE RESOURCES 2
SHEET 11: FPGA NO CONNECTS
SHEET 12: BOARD TO BOARD CONNECTOR
SHEET 13: 1P2V SUPPLY LEDS
SHEET 14: 1P8V AND 2P5V SUPPLY LEDS
SHEET 15: 3P3V AND 5V SUPPLY LEDS
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TLK10002EVM FPGA Daughterboard Schematics
13 TLK10002EVM FPGA Daughterboard Schematics
Figure 39. Cover Page and Index, Sheet 1 of 15
53
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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