Datasheet

www.ti.com EVM PCB and High-Speed Design Considerations
bidirectional, point-to-point data transmission systems such as base station RRH (remote radio head)
applications as well as any other high-speed application. All CPRI and OBSAI data rates from 1.2288
Gbps to 9.8304 Gbps and non-CPRI or OBSAI serial data rates between 1 Gbps and 10 Gbps are
supported for the high-speed side. Each channel of the TLK10002 can be operated from a single, shared
reference clock, or independently from separate reference clocks at different frequencies.
The TLK10002 performs data serialization/de-serialization and clock extraction as a physical layer
interface device. Flexible clocking schemes are provided to support various operations and include the
support for clocking with an externally jitter-cleaned clock recovered from the high-speed side.
Other features of the TLK10002 include an integrated latency measurement function, PRBS (2
7
- 1), (2
23
-
1), (2
31
- 1), and high, low, and mixed CRPAT long/short generation and verification for self-test,
system-level support. Low-speed and high-speed side loopback modes are provided for self-test and
system diagnostic purposes.
The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and
low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the
LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the
LOS condition to be cleared.
The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same
local physical system. The high-speed side is ideal for interfacing with remote systems through an optical
fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+
optical modules. Both FPGA and optical interfaces are available in the evaluation kit for rapid prototyping
and easy development.
Configuration of the TLK10002 on a per-channel basis is available by way of accessing a register space of
control bits available through a two-wire access port called the Management Data Input/Output (MDIO)
interface as defined in Clause 22 of the IEEE 802.3 Ethernet Specification.
(1)
The TLK10002EVM GUI
provides access to all the registers of every device used on any of the TLK10002 boards through a
standard USB 1.1 interface. The boards can be configured if necessary to accept or provide MDIO signals
from or to an external source by installing and uninstalling certain resistors.
The TLK10002EVM board can be run from a single, 5-V power supply or 5-Vdc transformer. All voltages
needed are regulated down through onboard LDO regulators which can be adjusted to the appropriate
minimum, nominal, and maximum values through changing a single resistor value.
Voltage monitor circuits with LEDs are included on all voltage rails for easy debugging and identification of
valid power rails.
All data I/O signals are broken out to connectors for easy and rapid prototyping; all control signals are
easily controlled through the GUI or shunts on header blocks.
2 EVM PCB and High-Speed Design Considerations
The board can be used to evaluate device parameters in addition to acting as a guide for high-speed
board layout. As the frequency of operation increases, the board designer must take special care to
ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled
to 50-Ω single-ended or 100-Ω differential impedance for both the low- and high-speed differential serial
and clock connections. Vias are minimized and, when necessary, are designed to minimize impedance
discontinuities along the transmission line. Care was taken to control trace length mismatch (board skew)
to less than ±0.5 mil.
Overall, the board layout must be designed and optimized to support high-speed operation. Thus,
understanding impedance control and transmission line effects are crucial when designing high-speed
boards. Some of the advanced features offered by this board include:
• The TLK10002 printed-circuit board (PCB) is designed for optimal high-speed signal integrity using
Rogers Material for the outer signal layers and FR-4 for the inner layers. All gigabit and clock signals
are routed over the Rogers Material for minimal signal loss. The optional FPGA and SMA Breakout
Daughterboards use FR-4 for all layers.
• SMA and header fixtures are easily connected to test equipment.
• All input/output signals are accessible for rapid prototyping.
(1)
The MDIO register map is located within the TLK10002 Dual-Channel 10Gbps Multi-Rate Transceiver datasheet.
5
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated