Datasheet

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
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REVISIONS
ECR
ECR NUMBER DATE
6522850
J. NERGER
G. ROTH
J. NERGER
TLK10002 EVM MOTHER BOARD
11/18/10
11/18/10
11/18/10 B NA
COVER PAGE AND NOTES
1 20
SIZE DOCUMENT NUMBER REV SHEET
of
ENGINEER
LAYOUT
RELEASED
DATE
DATE
DATE
SCHEMATIC TITLE
TEXAS INSTRUMENTS
PAGE TITLE
NOTES:
1. PLACE NET NAMES ON ALL JUMPERS AND HEADERS.
2. PLACE ALL PARTS OTHER THAN SMP CONNECTORS ON A 0 OR 90 DEGREE ORIENTATION.
3. SERIAL DATA SHOULD BE ROUTED AS SINGLE-ENDED 50 OHM TRANSM ISSION LINES ON OUTSIDE LAYERS. ROUTING DISTANCE SHOULD BE 3 INCHES OR LESS.
4. USE ROGERS MATERIAL FOR OUTSIDE LAYERS AND FR4-370 MATERI AL FOR INSIDE LAYERS.
5. SERIAL AND REFCLK NETS MUST MATCH WITHIN +/- 0.5 MILS
6. MATCH DIFFERENTIAL TRACE WIDTHS OF SERIAL AND REFCLK LINE S WITH SMP/SMA PADS.
7. PLACE TI LOGO IN TOP SIDE METAL
TLK10002 DATA SHEET REVISION: 0.7
DATA SHEET LAST UPDATED ON: 09/27/10
SCHEMATIC SHEET INDEX:
SHEET 01: TLK10002 CHAR COVER SHEET AND NOTES
SHEET 02: USB INTERFACE
SHEET 03: 1P0V, 1P5V, 1P8V REGULATORS
SHEET 04: 2P5V, 3P3V REGULATORS
SHEET 05: POWER DISTRIBUTION
SHEET 06: DEVICE POWER AND GROUND
SHEET 07: GLOBAL SIGNALS
SHEET 08: MDIO,JTAG, AND I2C INTERFACE
SHEET 09: CLOCKS
SHEET 10: JITTER CLEANER CONTROL
SHEET 11: LOW SPEED DATA SIGNALS
SHEET 12: HIGH SPEED DATA SIGNALS
SHEET 13: 1P0V, 2P0V, 3P3V REG LEDS
SHEET 14: 1P5V, 1P8V REG LEDS
SHEET 15: 5V, 3P3V PLL, AND VDDO LEDS
SHEET 16: VDDA, VDDT, VDDD, DVDD LEDS
SHEET 17: VDDRA LEDS
SHEET 18: VDDRB LEDS
SHEET 19: JITTER CLEANER POWER LEDS
SHEET 20: BOARD TO BOARD CONNECTOR
www.ti.com TLK10002EVM Motherboard Schematics
10 TLK10002EVM Motherboard Schematics
Figure 9. Cover Page and Index, Sheet 1 of 20
17
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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