Datasheet
O N
+ 5V
+ 5V
GND
1p8V
REG
1p5V
REG
3p3V
REG
EN
GND
EN
GND
EN
EN
GND
EN
GND
EN
GND
JITTER PLL
P 1
P 14
C 48
C 47
R 120
U 16
C 34
C 33
JM P9
U 12
R 86
JM P5
C 76
C 75
U 24
R 18 8
JMP 17
C 79
C 82
C 83
C 81
D 41
PLL_LOCK
GND
VCC _IN
JMP64
JMP 63 JMP 66
JMP 35
LE
CLK
MOSI
MISO
JMP 58
SPI
GND
VCCA
R 315
R 31 2
C 28 5
JMP 55
P WR _ D N
MD E_ S E L
R E F_ SE L
A UX_ S EL
P L L_ LC K
U 2
JITTER
CLEANER
AUXp
VDDRA_ HS
VCC_ OUT
VCXO
C 97
R537
R536
C 118 C 127 C 108 C 84
JMP 41
C 138
C 139
C 140
C 99
C 1 00
C 1 01
JM P7 3
C 1 23
C 124
C 1 25
JMP 75
C 12 8
C 12 9
C 13 0
J M P 71
C 11 3
C 11 4
C 11 5
J M P 74
C 8 9
C 9 0
C 9 1
J M P 72
U 10
P 2
VDDRB_ HS
1 p5V
1 p8V
VDDO
VDDRB_L S
VDDRA_L S
1p0V
DIGITAL
BJ
5V
PLUG
C 27
C 25
U 8
R69
R 52
C 20
C 18
JMP 1
1p0V
ANALOG
JMP 3
VDDD
GND
GND
GND
GND
GND
EN
DVDD VDDA VDDT
J M P6 9
JMP7 0
J M P6 7
JMP6 8
C 107 C117 C 80 C93
C 109
C 110
C 111
C 119
C 120
C 121
C 85
C 86
C 87
C 94
C 95
C 98
R494
C293
C294
R495
C245
C243
C247
J42
J41 J 44
J71
J70
C 26 4
AUXn
C 27 0
C 26 8
C 26 9
C 27 1
U 5 7
U 7 0
U 7 3
U 79
U7 6
J43
J 6
J 5
J 7
J8
J48
J 47
J 46
J45
JMP 76
J73
D 4 8
D 5 1
D 5 2
D 4 9
D 5 0
HSTXBn
HSTXBp
HSRXBp
HSRXBn
CLKOUTBn
U 1
J72
TLK10002 EVM
MOTHER BOARD
REV A
6522850
C 2 63
C 26 6
C 2 91
C 26 1
C 26 7
C 29 2
U 51
U 63
U 90
U4 5
U6 7
U 87
U 6 0
C 265
C 62
C 61
U 20
U 48
C 26 0
C 69
C 68
U2 2
JMP 13
JMP 43
JMP 15
J6 5
JMP 52
SW 3
R 4 1
R 4 8
R 4 0
R 4 2
C 12
R 43
C 13
C 14
SW 1
C1 0
C 6
R 35
R 44
R 36
U 5
R 10
R 1 8
C 2
D 2
D 1
U 7
R 1
R 2
C 1 1
R475
R 474
R 15
R 14
C 4
R 11
R 5
R 3
R 8
R 28
R 27
R 26
R 25
C 7
JM P5 0
D 4
D 3
ONLINE
SUSPEND
SW 2
JMP 47
JMP 62
R 3 07
R 30 6
C 30 2
D 35 D 36
D 40
D 34
D 38
D 26
D 39
D 33
D 37
D 25
D 46
D 47
D 44
D 45
D 31
D 32
D 29
D 30
D 17
D 18
D 21
D 22 1p8 V
1p5 V
1p0 V D
1 p0V A
V D D T
V D DA
D VDD
V DDD
JC _V C C A
J C_V C X O
J C_V C C _ O U T
J C_ VCC _ IN
V D D O
V D D R B_ LS
V D D R A_ LS
V D DRB _ H S
V D D R A_ H S
U42
U 41 U 64
D4 3
D4 2
SW 4
JMP 57
JMP 42
D 10 D 11
J M P 44
JMP 45
D 19
D 2 0
D 27
D 28 5V
3p 3V P
3p 3V
2p 5V
L O S A
L O S B
PRB S
PAS S
D 1 2
D 1 3
D 1 6
D 1 4LS A O K
LS B O K
D 1 5
JMP 4 8
G N D
LS O K O U TA
LS O K O U TB
G N D
JMP 61
3 p3 V
JMP 60
U 39
JMP 53
STCI _VCC
GND
SCANCLK
SCANCFG 0
SCANIN
SCANOUT
SCANCFG 1
JMP 46
P R TA D 0
P RT AD 1
P RT AD 2
P R TAD 3
P R TAD 4
G N D
LS
O KI N B
O KINA
LS
G ND
A M UX B
A M UX A
PRB S
PASS
LOSB
LOSA
G PI O
T E ST _E N
P RBS_ E N
C LKB _ SE L
C LK A_ S EL
PDTR X B
PDTR X A
SCL
SDA
RATE _ SEL _ 1
RATE _ SEL _ 0
MOD DETECT
RX _ LOS
TX _FAULT
TX _DISABLE
JITTER CLEANER
RESET
GND
JC
RST
GND
RST
RST
BTN
RESE T
RESE T
MAIN RESET
GND
MAIN
RST
2p5V REG
3p3 V RE G
USB RESET
RST
RST
GND
2p5 V
MDIOV
3p3 V
USB
MDIO
MDC
TRST
JTAG
GND
JTAG_V
3p3 V
RST
RST
STCI
USB
1 p5V 1p8V
T LK 1 00 02
TLK10 002
CLKOUTApCLKOUTAn
R
57
2
R
57
0
5
4
6
8
R
5
6
6
R
5
65
R
5
6
7
R
5
6
9
R
5
7
1
R
58
0
R
57
8
R
57
6
R
57
4
R
5
7
3
R
5
7
5
R
5
7
7
R
3
79
CLKOUTBp
C249
MO D D E TE C T
T X _F AU L T
R X _L O S
T X D I S AB L E
T X D I S AB L E
REFCLK1p
REFREF
CLK1nCLK0 p
REFCLK0n
G N D
I 2C
D IS A B LE
R 30 5
TLK10002 EVM SMA BREAKOUT DAUGHTER BOARD
6522852
REV A
J4 J5
J6
OUTB0P
OUTB0 N
OUTB3 N
J16
OUTB 3P
J17
J35
OUTA0 N
J34
OUTA0 P
J31
OUTA1 N
J30
OUTA1 P
GND
JM P5
GND
JMP2
LS_ OK_IN_A
LS_OK_OUT_A
LS_ OK_IN_B
LS_OK_OUT_ B
GND
GND
J2 J3
INB2P
J10
J11
INB2N
J8
J9
OUTB2N
J12
OUTB 2P
J13
J14
INB3P
J15
INB3 N
J33
INA0P
J32
INA0N
J23
OUTA3N
J22
OUTA3P
R
12
R11
CHB _CLKOUTP
JMP1
CHB_ CLKOUTN
R
1
8
R
17
R33
R34
I2C_SDA
I2C_SCL
J21
INA3P
J20
INA3N
R
19
R
2
0
J25
INA2P
R
2
3
R
2
4
J24
INA2N
J29
INA1P
J28
INA1 N
R
29
R
30
J26
OUTA2P
J27
OUTA2N
J37
CHA _CLKOUTN
J36
CHA_ CLKOUTP
R35
R3
6
R1
6
R
15
OUTB 1N
OUTB 1P
INB0NINB0P
R
2
R1
MDC_ POST_ LS
MDIO _POST_LS
MDIO _PRE_LS
MDC_PRE_LS
JMP3
JMP4
INB1 N
INB1 P
R
6
R
5
J7
J19
J18
GND
USB FOR
TLK10002 GUI
5VGND
SYSTEM BOARD THAT
NEEDS TO BE
OPTIMIZED
MDIO / MDC POST _LS
SIGNALS CONNECTED
TO SYSTEM BOARD
TL K 10 002
TL K10002
PRTAD 0
PRTAD 1
PRTAD 2
PRTAD 3
PRTAD 4
SET THE “PORT ADDR”
FIELD OF THE GUI TO
MATCH THE PRTAD [4:0]
OF THE SYSTEM BOARD
AND ENSURE IT IS
DIFFERENT THAN THE
PRTAD [4:0] OF THE EVM
MOTHER BOARD
MDC
M DIO
www.ti.com
Test and Setup Configurations
Figure 7. Optimizing the High-Speed Link of a System Board Through the GUI
15
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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