Datasheet
O N
+ 5V
+ 5V
GND1p8V
REG
1p5V
REG
3p3V
REG
EN
GND
EN
GND
EN
EN
GND
EN
GND
EN
GND
JITTER PLL
P1
P 14
C 48
C 47R 120
U 16
C 34
C 33
JMP 9
U 12
R 86
J MP 5
C 76
C 75
U24
R 188
JMP 17
C 79
C 82
C 83
C 81
D 41
PLL_LOCK
GND
VCC_IN
JMP64
JMP 63 JMP 66
JMP 35
LE
CLK
MOSI
MISO
JMP 58
SPI
GND
VCCA
R 315
R3 12
C 285
JMP 55
PWR_ D N
MD E _S E L
R E F_ S EL
A U X_ S EL
P LL_ LC K
U 2
JITTER
CLEANER
AUXp
VDDRA_HS
VCC_OUT
VCXO
C 97
R537
R536
C 118 C 127 C 108 C 84
JMP 41
C 138
C 139
C140
C 99
C 100
C 101
JMP 73
C 12 3
C 124
C 1 25
JMP 75
C 128
C 129
C 130
J M P 71
C 113
C 114
C 115
J M P 74
C 8 9
C 9 0
C 9 1
JM P72
U 10
P2
VDDRB_ HS
1p5V
1p8V
VDDO
VDDRB_ LS
VDDRA_ LS
1p0V
DIGITAL
BJ
5V
PLUG
C 27
C 25
U 8
R 69
R52
C20
C18
J MP 1
1p0 V
ANALOG
JMP 3
VDDD
GND
GND
GND
GND
GND
EN
DVDD VDDA VDDT
JM P69
JM P70
JM P67
JM P68
C 107 C 117 C 80 C 93
C 10 9
C 11 0
C 11 1
C 11 9
C 12 0
C 12 1
C 85
C 86
C 87
C 94
C 95
C 9 8
R494
C293
C294
R495
C245
C243
C247
J42
J 41 J44
J71
J 70
C 264
AUXn
C 27 0
C 2 68
C 2 69
C 27 1
U 57
U 70
U 73
U 79
U 7 6
J43
J 6
J5
J7
J8
J48
J47 J 46 J45
JMP 76
J73
D 4 8
D 5 1
D 5 2
D 4 9
D 5 0
HSTXBn
HSTXBp
HSRXBp
HSRXBn
CLKOUTBn
U 1
J72
TLK10002 EVM
MOTHER BOARD
REV A
6522850
C 26 3
C 266
C 29 1
C 26 1
C 26 7
C 2 92
U 5 1
U 6 3
U 9 0
U4 5
U6 7
U8 7
U 6 0
C2 65
C 62
C 61
U 20
U 4 8
C 260
C69
C68
U 22
JMP 13
JMP 43
JMP 15
J65
JMP 52
SW 3
R 4 1
R 48
R 40
R 42
C 12
R 43
C 13
C 14
SW 1
C 10
C 6
R 35
R 44
R 36
U 5
R 1 0
R 18
C 2
D2
D 1
U 7
R 1
R 2
C11
R475
R474
R 15
R14
C 4
R11
R 5
R 3
R 8
R2 8
R2 7
R2 6
R2 5
C 7
JMP 50
D 4
D 3
ONLINE
SUSPEND
SW 2
JMP 47
JMP 62
R 3 07
R 3 06
C 3 02
D 35 D 36
D 40
D 34
D 38
D 26
D 39
D 33
D 37
D 25
D 46
D 47
D 44
D 45
D 31
D 32
D 29
D 30
D 17
D 18
D 21
D 22 1p8 V
1p5 V
1p0VD
1p0 VA
VDD T
VDD A
D V DD
V D D D
JC_ V C C A
JC _V C X O
JC _V C C _OU T
JC _V C C _IN
V D DO
V D DRB _L S
V D DRA _L S
V D DRB _H S
V D DRA _H S
U 42
U 41 U 64
D 43
D 42
SW 4
JMP 57
JMP 42
D 10 D 11
JM P44
JMP 45
D1 9
D2 0
D2 7
D2 8 5 V
3 p3V P
3 p3V
2 p5V
L OS A
LOSB
P RBS
P AS S
D 1 2
D 1 3
D 1 6
D 1 4
LS A O K
LS B O K
D 1 5
JM P4 8
G N D
L S O K O U TA
L S O K O U TB
G N D
JMP 6 1
3p 3V
JMP 60
U 39
JMP 53
STCI _VCC
GND
SCANCLK
SCANCFG 0
SCANIN
SCANOUT
SCANCFG 1
JMP 46
PRT A D 0
PRT A D1
PRT A D2
PRT A D3
PRT A D4
G N D
LS
OK I N B
OK I N A
LS
GN D
AMU X B
AMU X A
PRB S
PAS S
LOS B
LOS A
GP I O
TE ST _E N
PRB S _EN
C L KB _S E L
C L K A_SE L
P D TR X B
P D TR X A
SCL
SDA
RATE _SEL _1
RATE _SEL _0
MOD DETECT
RX _LOS
TX_ FAULT
TX _ DISABLE
JITTER CLEANER
RESET
GND
JC
RST
GND
RST
RST
BTN
RESE T
RESE T
MAIN RESET
GND
MAIN
RST
2p 5VREG3p3V REG
USB RESET
RST
RST
GND
2p5V
MDIOV
3p3V
USB
M DI O
M DC
T RST
JTAG
GND
JTAG_V
3p 3V
RST
RST
STCI
USB
1 p5V 1p 8V
TL K 10 002
T LK10002
CLKOUTApCLKOUTAn
R
57
2
R
57
0
5
46
8
R
56
6
R5
65
R
5
67
R
5
6
9
R5
71
R5
80
R5
7
8
R
5
7
6
R5
7
4
R
57
3
R
57
5
R
57
7
R3
7
9
CLKOUTBpC249
MO D D E TE C T
TX _F A ULT
RX _L O S
TX D IS A BLE
TX D IS A BLE
REFCLK1p
REFREF
CLK1nCLK0 p
REFCLK0n
GN D
I2 C
D IS A BL E
R 30 5
O N
X C F32 P
FG48
JMP 7
P3
TLK10002 EV M
FPGA DAUGHTER BOARD
REV A 6522851
P1
P2
+5V
+5V
PLUG
+5V
BJ
C 54
C55
C 56
C47 R62
R 65
R 64
R 60
C 44
C 45
R54
R52
R46
R49
C 33
C 30
C 29
Q 17
U9
U10
Q 19
1 P2V GTP
G ND
EN
L3C 57
C 60
JMP3
JMP 31
GND
EN
JM P6
1P2 V REG
L4C 61
C64
JMP 32
C 38
C 39
R 58
R 63
R 66
3P3 VREG
U11
C 46
R 61
J MP 5
GND
EN
Q 18
U8
2P5 VREG
Q 16
R 48
JMP 2
C32
R5 3
R5 1
R4 4
C2 4
C 23
GND
EN
GND
EN
1P8V RE G
L 1
C 48
C 51
J M P3 0
C 17
C 18
R4 2
R5 0
R 56
C 3 1
Q 15
R 47
J MP 1
U7
CLK1
JMP 4
1P 8V
D4 6
D4 7
V C CO_1 P 8V
U 37
C 243
U 36 U39 U42 U 30 U33
C 242C 241C 245C 244
U4 0
U 43
U3 1
U3 4
D4 5
D4 4
D4 3
D4 2
D5 1
D5 0
D4 9
D4 8
2P 5 V
V C C AUX _2 P5 V
3P 3 V
V C C CL K _3 P3V
1P 2V
V C C I NT _1 P2V
1P2 V _G TP
VCC M G T _1 P2V
GND
JMP14
JMP13
CHB_CLKN CHB_ CLKP
IO_SIGNALS
0
1
2
3
4
5
6
7
8
9
10
1 1
12
13
1 4
1 5
16
17
1 8
1 9
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
JMP22IO SIGNA LS
GND
CL K2
FPGA
RE-PROGRAM
GCLK2 5GCLK27GCLK 12GCLK17
J11
J10
J9
J7
SW 5
USB
USB
J2
RESET
SW6
MAIN RESET
PB4RESETPB3RESETPB2 RESETPB1RESET
SW1 SW2 SW3
SW4 SW8
MDIO RESET
GCL K14
SW9
J8
CHA_CLKp CHA_CLKn
JMP21
JMP15
JMP9
JTAG
U44
JM P21
J4 J6
SW7
GND
GND
SDA
I2C
1
G P I O_1
G P I O_2
G PI O_3
G PI O_4
G PI O_5
JMP33
C67
C 65
L 5
JMP 11
C 21
C 213
C 217
SMA
CHB _CLK _SEL
TLK CLK
L6
C69 D 21
C 72
D 18
JM P3 4
R 70
PROG _B _ RST
R 67
R 74
R 80
R 81
R 75
PROG _B _ /RST
JM P8
U 13 C200
R 78
JMP 23
R 267
R 266
R 265
R 243
R37 7
HSWAPEN
J M P 36
J M P 18
R 26 4
GND
C212
C211
C218
TLK CLK
CHA _CLK _SEL
SMA
JMP 10
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
C 154
C 160
C 156
C 148
C 173
C 164
C 157
C 149
C 259 R88
R89
R86
R84
R 83
R 385
R 386
R 381
R 87
R 85
R 82
C 2 46
1 3 5
C 2 35
C 24 7
R77
R91
C256
C255
A
C
E
G
2 4
6
B
D
F
H
R 76
R 79
JMP 29
C 12
C 11
C 10
R 30
R 40
R 31
R 32
R 25 R34
C 8
R 33
R 26
R 10
C 2
C 5
R 8
R5
U5
C 1
R 38
R 39
R9
R6
R3
D1 4
U S B_ R ST
R2
U 6
D 13
D 16
D 15
U S B_ ON L I N E
U SB_ SU S P
C 4
R 35 1
R 20 1
R 20 2
R 3 52
U SB_ /RST
R 1
C 9
R 134
R 213
C 236
C 26 1
R 21 2
C 2 33
Q 32 Q 31
2P 5V
MDIO
3P 3V
JMP 20
R 19 9
R 197
R 200
R 198 R 206 R 205
JMP 28JMP 19
MD C
MD I O
MD C
MD I O
R 1 32
C 24 0
JMP 12
U 16
D 22 D 23
R 1 31
RS T
RS T
LS _ OK _IN _B
D2 6
LS _ OK _OU T_ B
R 173
D2 7
R 174
L S_ O K_ O U T_A
D2 5
R 172
L S_ OK _ IN_ A
D2 4
R 171
LE D 1
R2 89
U 27
JMP 27
D 39 D40
R2 95
R 28 7
RS T
RS T
PB3
RS T
RS T
PB4
RS T
RS T
PB2
R S T
RS T
PB1
D1
R 242
R 240
L ED 2
D2
LE D 3
D3
R 238
L ED 4
D4
R 236
LE D 5
D5 R 234
R 29 2
R 28 5
LE D 6
D6
R 232
L ED 7
D7
R 230
L ED 8
D8
R 238
LE D 9
D9
R 226
L ED 10
R2 76
R 27 1
R 27 8
R 26 9
D1 0
R 224
L ED 11
R 222
D 11
LE D 12
D12
R 232
D ON E
R 69
D 19
D 20
JMP 24
D34 D 36
U21
JMP 25
D 35 D37
JMP 26
U23
D38 D41
U25
C 2 39
R2 88
C 23 8
R2 73
C 2 37
R2 72
R 3 83
R 68
Q 21
/ INIT _B
Q 3 4
D 53
/B U SY
D 28
R175
LOSA
LOSB
LOSA
LOSB
D 29
R 176
TEST _PASS _A
TST _PASS _ A
D 30
R 177
TEST _PASS _B
D 31
R178
TST _PASS _B
JMP 35
R 191
D 33
D 32
RST
RST
MDIO
R 188
R189
SUS PE N D ED
D 5 4
R 39 8
U18
C 234
LOOPBACK _A
P R TA D 4
U1
C 25 1
R 36 5
R 36 2
R 36 3
R 36 6
R 36 1
R 36 4
C 25 3
5V
D 52
GND
REG
REG
U 4 8
D5 5
VIN T_ 1P 8V
JMP 37
GND
GND
V CCI N T _1P 8V
VCCO _1 P8 V
GND
VCCMGT _1 P2 VVCCINT _1P 2V
JMP 17JMP 16
GND
CLK 1
GND
VCCAUX _ 2P 5V
GND
VCCCLK _3 P 3V
G N D
PROG _B
C 282
U 47
G N D
MD I O R S T
GND
GND
PB1
RST
GND
PB2
RST
GND
PB3
RST
GND
PB4
RST
GND
MAIN
RST
GNDGND
PRE _LS
POST _ LS
R 21 4
T DI
T DO
VCCAUX_2P5V
T MS
TCK
P R TA D 0
P R TA D 1
P R TA D 2
P R TA D 3
J3J5
C 23 2
C
22 5
C 2 30
C2 28
C2 22
C 2 24
C2 20
C2 15
C 2 06
C2 05
X ILINX
SPA RTAN -6
XC6SLX75 T
25
23
21
1 9
5 3 19 7
C 227
C 229
C 223
C 221
C 216
C 204
C 219
C 208
U 14
U 15
C
22 6
C
2
31
PDTRXA _ N
PRBSEN
TEST _EN _A
TEST _EN _B
G N D
LANE 2_4 _SELECT _ A
LANE 2_4 _SELECT _ B
LOOPBACK _B
C207
C202
R
40
5
R
4
0
6
R
40
3
R
4
04
R
40
1
R4
02
R
3
9
9
R
4
00
SCL
C201
C203
R
4
1
2
R
4
11
R
4
1
0
R
4
09
R
4
1
6
R
4
1
7
R
41
8
R
4
1
3
5V5V GNDGND 122.88MHz
122.88MHz
USB FOR
TLK10002 GUI
XILINX JTAG
PROGRAMMING
INTERFACE
SFP+ MODULE
WITH LOOPBACK
122.88MHz
Test and Setup Configurations
www.ti.com
Figure 6. CRPAT Test Setup With FPGA Generator and Verifier
It is possible to use the Link Optimizer portion of the TLK10002 GUI to optimize the high-speed link on a
third-party system board. Connect the TLK10002EVM SMA to the TLK10002EVM motherboard and
connect the MDC_POST_LS and MDIO_POST_LS signals from the breakout board to the system board.
Ensure that the system PRTAD[4:0] address is different than the motherboard’s PRTAD[4:0], and enter
the system address in the Port Addr field on the Low Level Register Configuration tab of the
TLK10002EVM GUI.
14
TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module SLLU148– May 2011
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