Datasheet
ON
+ 5V
+ 5V
GND
1p8V
REG
1p5V
REG
3p3V
REG
EN
GND
EN
GND
EN
EN
GND
EN
GND
EN
GND
JITTER PLL
P1
P14
C48
C47
R120
U16
C34
C33
JMP9
U12
R86
JMP5
C76
C75
U24
R188
JMP17
C79
C82
C83
C81
D41
PLL_LOCK
GND
VCC_IN
JMP64
JMP63
JMP66
JMP35
LE
CLK
MOSI
MISO
JMP58
SPI
GND
VCCA
R315
R312
C285
JMP55
PWR_DN
MDE_SEL
REF_SEL
AUX_SEL
PLL_LCK
U2
JITTER
CLEANER
AUXp
VDDRA_HS
VCC_OUT
VCXO
C97
R537
R536
C118 C127
C108 C84
JMP41
C138
C139
C140
C99
C100
C101
JMP73
C123
C124
C125
JMP75
C128
C129
C130
JMP71
C113
C114
C115
JMP74
C89
C90
C91
JMP72
U10
P2
VDDRB_HS
1p5V
1p8V
VDDO
VDDRB_LS
VDDRA_LS
1p0V
DIGITAL
BJ
5V
PLUG
C27
C25
U8
R69
R52
C20
C18
JMP1
1p0V
ANALOG
JMP3
VDDD
GND
GND
GND
GND
GND
EN
DVDD VDDA
VDDT
JMP69
JMP70
JMP67
JMP68
C107 C117 C80 C93
C109
C110
C111
C119
C120
C121
C85
C86
C87
C94
C95
C98
R494
C293
C294
R495
C245
C243
C247
J42
J41 J44
J71
J70
C264
AUXn
C270
C268
C269
C271
U57
U70
U73
U79
U76
J43
J6
J5
J7
J8
J48
J47
J46
J45
JMP76
J73
D48
D51
D52
D49
D50
HSTXBn
HSTXBp
HSRXBp
HSRXBn
CLKOUTBn
U1
J72
TLK10002 EVM
MOTHER BOARD
REV NA
6522850
C263
C266
C291
C261
C267
C292
U51
U63
U90
U45
U67
U87
U60
C265
C62
C61
U20
U48
C260
C69
C68
U22
JMP13
JMP43
JMP15
J65
JMP52
SW3
R41
R48
R40
R42
C12
R43
C13
C14
SW1
C10
C6
R35
R44
R36
U5
R10
R18
C2
D2
D1
U7
R1
R2
C11
R475
R474
R15
R14
C4
R11
R5
R3
R8
R28
R27
R26
R25
C7
JMP50
D4
D3
ONLINE
SUSPEND
SW2
JMP47
JMP62
R307
R306
R305
D35
D36
D40
D34
D38
D26
D39
D33
D37
D25
D46
D47
D44
D45
D31
D32
D29
D30
D17
D18
D21
D22
1p8V
1p5V
1p0VD
1p0VA
VDDT
VDDA
DVDD
VDDD
JC_VCCA
JC_VCXO
JC_VCC_OUT
JC_VCC_IN
VDDO
VDDRB_LS
VDDRA_LS
VDDRB_HS
VDDRA_HS
U42
U41
U64
D43
D42
SW4
JMP57
JMP42
D10 D11
JMP44
JMP45
D19
D20
D27
D28
5V
3p3VP
3p3V
2p5V
LOSA
LOSB
PRBS
PASS
D12
D13
D16
D14
LS A OK
LS B OK
D15
JMP48
GND
LSOK OUTA
LSOK OUTB
GND
JMP61
3p3V
JMP60
U39
JMP53
STCI_VCC
GND
SCANCLK
SCANCFG0
SCANIN
SCANOUT
SCANCFG1
JMP46
PRTAD0
PRTAD1
PRTAD2
PRTAD3
PRTAD4
GND
LS
OKINB
OKINA
LS
GND
AMUXB
AMUXA
PRBS
PASS
LOSB
LOSA
GPIO
TEST_EN
PRBS_EN
CLKB_SEL
CLKA_SEL
PDTRXB
PDTRXA
SCL
SDA
RATE_SEL_1
RATE_SEL_0
MOD DETECT
RX_LOS
TX_FAULT
TX_DISABLE
JITTER CLEANER
RESET
GND
JC
RST
GND
RST
RST
BTN
RESET
RESET
MAIN RESET
GND
MAIN
RST
2p5V REG
3p3V REG
USB RESET
RST
RST
GND
2p5V
MDIOV
3p3V
USB
MDIO
MDC
TRST
JTAG
GND
JTAG_V
3p3V
RST
RST
STCI
USB
I2C
DISABLE
1p5V
1p8V
TLK10002
TLK10002
CLKOUTAp
CLKOUTAn
C
2
4
0
C
2
3
6
C
2
3
2
C
2
2
8
C
2
2
6
C
2
3
0
C
2
3
4
C
2
3
8
C
2
4
1
C
2
3
7
C
2
3
3
C
2
2
9
C
2
2
7
C
2
3
1
C
2
3
5
C
2
3
9
CLKOUTBp
C249
MOD DETECT
TX_FAULT
RX_LOS
TX DISABLE
TX DISABLE
REFCLK1p
REFREF
CLK1nCLK0p
REFCLK0n
ON
XCF32P
FG48
JMP7
P3
TLK10002 EVM
FPGA DAUGHTER BOARD
REV NA 6522851
P1
P2
+5V
+5V
PLUG
+5V
BJ
C54
C55
C56
C47
R62
R65
R64
R60
C44
C45
R54
R52
R46
R49
C33
C30
C29
Q17
U9
U10
Q19
1P2V GTP
GND
EN
L3
C57
C60
JMP3
JMP31
GND
EN
JMP6
1P2V REG
L4C61
C64
JMP32
C38
C39
R58
R63
R66
JMP17
3P3V REG
U11
C46
R61
JMP5
GND
EN
Q18
U8
2P5V REG
Q16
R48
JMP2
C32
R53
R51
R44
C24
C23
GND
EN
GND
EN
1P8V REG
L1
C48
C51
JMP30
C17
C18
R42
R50
R56
C31
Q15
R47
JMP1
U7
JMP16
GND
CLK1
JMP4
R55
1P8V
D46
D47
VCCO_1P8V
U37
C243
U36
U39
U42
U30
U33
C242
C241C245C244
U40
U43
U31
U34
D45
D44
D43
D42
D51
D50
D49
D48
2P5V
VCCAUX_2P5V
3P3V
VCCCLK_3P3V
1P2V
VCCINT_1P2V
1P2V_GTP
VCCMGT_1P2V
GND
JMP14
JMP13
CHB_CLKN CHB_CLKP
IO_SIGNALS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
JMP22
IO SIGNALS
GND
CLK1
FPGA
RE-PROGRAM
GCLK25GCLK27
GCLK12
GCLK17
J11
J10
J9
J7
SW5
USB
USB
J2
RESET
SW6
MAIN RESET
PB3 RESETPB4 RESETPB2 RESETPB1 RESET
SW1 SW2 SW3
SW4 SW8
MDIO RESET
GCLK14
SW9
J8
CHA_CLKp
CHA_CLKn
JMP21
JMP15
JMP9
JTAG
U44
JMP21
J4 J6
SW7
GND
GND
SDA
I2C
1
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
JMP33
C67
C65
L5
JMP11
C21
C213
C217
SMA
CHB_CLK_SEL
TLK CLK
L6
C69
D21
C72
D18
JMP34
R70
PROG_B_RST
R67
R74
R80
R81
R75
PROG_B_/RST
JMP8
U13
C200
R78
JMP23
R267
R266
R265
R243
R377
HSWAPEN
JMP36
JMP18
R264
GND
C212
C211
C218
TLK CLK
CHA_CLK_SEL
SMA
JMP10
25
5 3 1
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
C154
C160
C156
C148
C173
C164
C157
C149
C259
R88
R89
R86
R84
R83
R385
R386
R381
R87
R85
R82
C246
1 3 5
C235
C247
R77
R91
C256
C255
A
C
E
G
2 4
6
B
D
F
H
R76
R79
JMP29
C12
C11
C10
R30
R40
R31
R32
R25 R34
C8
R33
R26
R10
C2
C5
R8
R5
U5
C1
R38
R39
R9
R6
R3
D14
USB_RST
R2
U6
D13
D16
D15
USB_ONLINE
USB_SUSP
C4
R351
R201
R202
R352
USB_/RST
R1
C9
R134
R214
R213
C236
C261
R212
C233
Q32 Q31
2P5V
MDIO
3P3V
JMP20
R199
R197
R200
R198 R206
R205
JMP28JMP19
MDC_CON
MDIO_CON
MDC
MDIO
R132
C240
JMP12
U16
D22 D23
R131
RST
RST
LED9
D9
LED10
R226
D10
R224
LS_OK_IN_B
D26
R173
LED8
D8
R228
LS_OK_OUT_B
R289
U27
JMP27
D39
D40
R295
R287
RST
RST
PB3
RST
RST
PB4
RST
RST
PB2
RST
RST
PB1
D27
R174
R242
LED1
D1
LED12
D12
R220
LED11
D11
R222
LED2
D2
R240
R292
R285
LS_OK_OUT_A
D25
R172
LED3
D3
R238
LED4
D4
R236
LS_OK_IN_A
D24
R171
LED7
R276
R271
R278
R269
D7
R230
LED6
R234
D5
LED6
D6
R232
DONE
R69
D19
D20
JMP24
D34
D36
U21
JMP25
D35 D37
JMP26
U23
D38 D41
U25
C239
R288
C238
R273
C237
R272
D52
5V
R383
R68
Q21
/INIT_B
Q34
D53
/BUSY
D28
R175
LOSA
LOSB
LOSA
LOSB
D29
R176
TEST_PASS_A
TST_PASS_A
D30
R177
TEST_PASS_B
D31
R178
TST_PASS_B
JMP35
R191
D33
D32
RST
RST
MDIO
R188
R189
SUSPENDED
D54
R398
U18
C234
XILINX
SPARTAN-6
XC6SLX75T
C201
C203
C207
C202
PDTRXA_N
PRBSEN
TEST_EN_A
TEST_EN_B
GND
LANE2_4_SELECT_A
LANE2_4_SELECT_B
LOOPBACK_A
LOOPBACK_B
SCL
VCCAUX_2P5V
TMS
TCK
TDO
TDI
PRTAD0
PRTAD1
PRTAD2
PRTAD3
PRTAD4
23
21
19
C230
C228
C222
C224
C220
C215
C206
C205
9 7
U14
J3
J5
C
232
C
2
25
U1
C251
R365
R362
R363
R366
R361
R364
C253
C227
C229
C223
C221
C216
C204
C219
C208
U15
C226
C
231
www.ti.com
Test and Setup Configurations
Figure 5. TLK10002EVM Motherboard and FPGA Daughterboard
A common method of evaluating the TLK10002 is to place the TLK10002 device in the transceiver mode
with its high-speed signals externally looped back to itself. Using an external data source to generate and
verify the data on the low-speed side of the device, data fully passes through the TLK10002 device exactly
as it does in a system application.
Figure 6 is a diagram of how to set up the TLK10002 motherboard and the FPGA daughterboard that uses
the FPGA CRPAT generators and verifiers to evaluate the TLK10002. The same 122.88-MHz clock must
be applied to both FPGA clock inputs as well as one of the TLK10002 reference clock inputs. Two 5-V
power supplies are needed, and 5 V must be applied to both boards individually because no power is
shared through the board-to-board connector. Channel B of the TLK10002 must have SMA cables
connected as shown with TXBP/RXBP and TXBN/RXBN connected together. In order to evaluate Channel
A, an SFP+ Optical Module and optical fiber are required. A single USB cable connected to the TLK10002
motherboard allows access to the registers of both boards. Note that the PRTAD device address pins of
the TLK10002 boards must be different in order to prevent writing to the wrong device’s registers. The
TLK10002 motherboard comes configured with PRTAD equal to address “0” and the FPGA daughterboard
is configured with the address of “1.” In order communicate with the FPGA registers in the TLK10002EVM
GUI, the PRTAD address of the FPGA daughterboard must first be entered into the Port Addr field on the
Low Level Register Configuration tab and changed back to the TLK10002 address prior to re-accessing
the TLK10002 registers.
13
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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Copyright © 2011, Texas Instruments Incorporated