Datasheet

ON
XCF32P
FG48
JMP7
P3
TLK10002 EVM
FPGA DAUGHTER BOARD
REV NA 6522851
P1
P2
+5V
+5V
PLUG
+5V
BJ
C54
C55
C56
C47
R62
R65
R64
R60
C44
C45
R54
R52
R46
R49
C33
C30
C29
Q17
U9
U10
Q19
1P2V GTP
GND
EN
L3
C57
C60
JMP3
JMP31
GND
EN
JMP6
1P2V REG
L4C61
C64
JMP32
C38
C39
R58 R63 R66
JMP17
3P3V REG
U11
C46
R61
JMP5
GND
EN
Q18
U8
2P5V REG
Q16
R48
JMP2
C32
R53
R51
R44
C24
C23
GND
EN
GND EN
1P8V REG
L1
C48
C51
JMP30
C17
C18
R42 R50
R56
C31
Q15
R47
JMP1
U7
JMP16
GND
CLK1
JMP4
R55
1P8V
D46 D47
VCCO_1P8V
U37
C243
U36
U39
U42
U30
U33
C242
C241C245C244
U40
U43
U31
U34
D45
D44
D43 D42 D51 D50 D49 D48
2P5V
VCCAUX_2P5V
3P3V
VCCCLK_3P3V
1P2V
VCCINT_1P2V
1P2V_GTP
VCCMGT_1P2V
GND
JMP14
JMP13
CHB_CLKN CHB_CLKP
IO_SIGNALS
0 1
2 3
4
5 6 7 8 9
10
11
12 13
14 15
16 17
18 19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
JMP22
IO SIGNALS
GND
CLK1
FPGA
RE-PROGRAM
GCLK25GCLK27
GCLK12
GCLK17
J11
J10
J9
J7
SW5
USB
USB
J2
RESET
SW6
MAIN RESET
PB3 RESETPB4 RESETPB2 RESETPB1 RESET
SW1 SW2 SW3
SW4 SW8
MDIO RESET
GCLK14
SW9
J8
CHA_CLKp
CHA_CLKn
JMP21
JMP15
JMP9
JTAG
U44
JMP21
J4 J6
SW7
GND
GND
SDA
I2C
1
GPIO_1 GPIO_2
GPIO_3
GPIO_4
GPIO_5
JMP33
C67
C65
L5
JMP11
C21
C213
C217
SMA
CHB_CLK_SEL
TLK CLK
L6
C69
D21
C72
D18
JMP34
R70
PROG_B_RST
R67
R74
R80
R81
R75
PROG_B_/RST
JMP8
U13
C200
R78
JMP23
R267
R266
R265
R243
R377
HSWAPEN
JMP36
JMP18
R264
GND
C212
C211
C218
TLK CLK
CHA_CLK_SEL
SMA
JMP10
25
5 3 1
A
C
E
G
J
L
N
R
U
W
AA
AC
AE
C154
C160
C156
C148
C173
C164
C157
C149
C259
R88
R89
R86
R84
R83
R385
R386
R381
R87
R85
R82
C246
1 3 5
C235
C247
R77
R91
C256
C255
A
C
E
G
2 4
6
B
D
F
H
R76
R79
JMP29
C12
C11
C10
R30 R40 R31 R32
R25 R34
C8
R33
R26
R10
C2
C5
R8
R5
U5
C1
R38
R39
R9
R6
R3
D14
USB_RST
R2
U6
D13
D16 D15
USB_ONLINE
USB_SUSP
C4
R351 R201 R202
R352
USB_/RST
R1
C9
R134
R214 R213
C236
C261
R212
C233
Q32 Q31
2P5V
MDIO
3P3V
JMP20
R199
R197
R200
R198 R206
R205
JMP28JMP19
MDC_CON
MDIO_CON
MDC
MDIO
R132
C240
JMP12
U16
D22 D23
R131
RST RST
LED9
D9
LED10
R226
D10
R224
LS_OK_IN_B
D26
R173
LED8
D8
R228
LS_OK_OUT_B
R289
U27
JMP27
D39
D40
R295
R287
RST
RST
PB3
RST
RST
PB4
RST
RST
PB2
RST
RST
PB1
D27
R174
R242
LED1
D1
LED12
D12
R220
LED11
D11
R222
LED2
D2
R240
R292
R285
LS_OK_OUT_A
D25
R172
LED3
D3
R238
LED4
D4
R236
LS_OK_IN_A
D24
R171
LED7
R276
R271
R278
R269
D7
R230
LED6
R234
D5
LED6
D6
R232
DONE
R69
D19
D20
JMP24
D34
D36
U21
JMP25
D35 D37
JMP26
U23
D38 D41
U25
C239
R288
C238
R273
C237 R272
D52
5V
R383
R68
Q21
/INIT_B
Q34
D53
/BUSY
D28
R175
LOSA
LOSB
LOSA
LOSB
D29
R176
TEST_PASS_A
TST_PASS_A
D30
R177
TEST_PASS_B
D31
R178
TST_PASS_B
JMP35
R191
D33
D32
RST
RST
MDIO
R188
R189
SUSPENDED
D54
R398
U18
C234
XILINX
SPARTAN-6
XC6SLX75T
C201
C203
C207 C202
PDTRXA_N
PRBSEN
TEST_EN_A
TEST_EN_B
GND
LANE2_4_SELECT_A
LANE2_4_SELECT_B
LOOPBACK_A
LOOPBACK_B
SCL
VCCAUX_2P5V
TMS
TCK
TDO
TDI
PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4
23
21
19
C230
C228 C222
C224
C220 C215
C206
C205
9 7
U14
J3
J5
C
232
C
225
U1
C251 R365 R362 R363 R366 R361 R364 C253
C227
C229
C223
C221 C216 C204 C219
C208
U15
C
226
C231
www.ti.com Test and Setup Configurations
Figure 3. TLK10002EVM FPGA Daughterboard
11
SLLU148– May 2011 TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver Evaluation Module
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