Datasheet
TLE4275-Q1
www.ti.com
SLVS647H –AUGUST 2006–REVISED MARCH 2013
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
IN –42 45
V
I
Input voltage range
(2)
V
DELAY –0.3 7
OUT –1 16
V
O
Output voltage range V
RESET –0.3 25
I
I
Input current DELAY ±2 mA
I
O
Output current RESET ±5 mA
T
J
Operating junction temperature range –40 150 °C
T
stg
Storage temperature range –65 150 °C
Human-body model (HBM)
(3)
6000
ESD Electrostatic discharge rating V
Machine model (MM)
(4)
400
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
(3) HBM ESD rating tested per JESD22-A114.
(4) MM ESD rating tested per JESD22-A115.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
I
Input voltage 5.5 42 V
T
J
Junction temperature –40 150 °C
THERMAL INFORMATION
TLE4275-Q1
THERMAL METRIC
(1)
KTT KVU PWP UNIT
5 PINS 5 PINS 20 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
28.8 40.3 39.3 °C/W
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
43.1 31.8 22.7 °C/W
θ
JB
Junction-to-board thermal resistance
(4)
0.8 17.2 19.1 °C/W
ψ
JT
Junction-to-top characterization parameter
(5)
3.7 2.8 0.6 °C/W
ψ
JB
Junction-to-board characterization parameter
(6)
0.7 17.1 18.9 °C/W
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
0.2 0.7 1.5 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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