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TLE2141-Q1

www.ti.com

SLOS525 –SEPTEMBER 2011

Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIERS

Check for Samples: TLE2141-Q1

FEATURES

• Qualified for Automotive Applications

• Low V

… 500 μV (Max) at 25°C

• Low Noise • Single or Split Supply … 4 V to 44 V

– 10 Hz … 15 nV/√Hz • Fast Settling Time

– 1 kHz … 10.5 nV/√Hz – 340 ns to 0.1%

• 10000-pF Load Capability – 400 ns to 0.01%

• 20-mA Min Short-Circuit Output Current • Saturation Recovery … 150 ns

• 27-V/μs Slew Rate (Min) • Large Output Swing …

CC–

+ 0.1 V to V

CC+

– 1 V

• High Gain-Bandwidth Product … 5.9 MHz

DESCRIPTION

The TLE2141-Q1 device is a high-performance, internally compensated operational amplifier built using the

Texas Instruments complementary bipolar Excalibur™ process. It is a pin-compatible upgrade to standard

industry products.

The design incorporates an input stage that simultaneously achieves low audio-band noise of 10.5 nV/√Hz with a

10-Hz 1/f corner and symmetrical 40-V/μs slew rate typically with loads up to 800 pF. The resulting low distortion

and high power bandwidth are important in high-fidelity audio applications. A fast settling time of 340 ns to 0.1%

of a 10-V step with a 2-kΩ/100-pF load is useful in fast actuator/positioning drivers. Under similar test conditions,

settling time to 0.01% is 400 ns.

The device is stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz at

this high loading level. As such, the TLE2141-Q1 is useful for low-droop sample-and-holds and direct buffering of

long cables, including 4-mA to 20-mA current loops.

The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as

is evidenced by a 500-μV maximum offset voltage and 1.7-μV/°C typical drift. Minimum common-mode rejection

ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.

Device performance is relatively independent of supply voltage over the ±2-V to ±22-V range. Inputs can operate

between V

CC–

– 0.3 V to V

CC+

– 1.8 V without inducing phase reversal, although excessive input current may flow

out of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearly

rail-to-rail output swing of V

CC–

– 0.1 V to V

CC+

– 1 V under light current-loading conditions. The device can

sustain shorts to either supply since output current is internally limited, but care must be taken to ensure that

maximum package power dissipation is not exceeded.

The TLE2141-Q1 device can also be used as a comparator. Differential inputs of V

CC±

can be maintained without

damage to the device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good

indication as to output stage saturation recovery when the device is driven beyond the limits of recommended

output swing.

The TLE2141-Q1 device is available in industry-standard 8-pin package. The device is characterized for

operation from –40°C to 125°C.

ORDERING INFORMATION

(1)

PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

–40°C to 125°C SOIC – D (8 pin) Reel of 2500 TLE2141QDRQ1 2141Q

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Excalibur is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIERS Check for Samples: TLE2141-Q1 FEATURES 1 • • 2 • • • • Qualified for Automotive Applications Low Noise – 10 Hz … 15 nV/√Hz – 1 kHz … 10.5 nV/√Hz 10000-pF Load Capability 20-mA Min Short-Circuit Output Current 27-V/μs Slew Rate (Min) High Gain-Bandwidth Product … 5.9 MHz • • • • • Low VIO … 500 μV (Max) at 25°C Single or Split Supply … 4 V to 44 V Fast Settling Time – 340 ns to 0.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.
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Copyright © 2011, Texas Instruments Incorporated OFFSET N2 OFFSET N1 IN + IN - Q1 R2 Q3 R1 Q2 Q4 D1 Q7 Q6 R3 R5 Q12 Q11 R6 Q10 Q9 C1 Q5 Q8 R4 Q14 D2 R9 VCC - Q18 Q19 R12 Q20 Q21 C4 24 8 4 1 Resistors Diodes Capacitors Epi-FET TLE2141-Q1 46 COMPONENT R13 D4 C3 DEVICE COMPONENT COUNT R11 C2 D3 Q22 R14 Q24 D5 Q25 R16 R15 Q23 Q29 D7 D6 Q28 R17 Q27 Q26 R18 D8 R20 Q33 Q32 Q31 Q30 R19 R22 Q35 Q36 R23 Q34 R21 Q37 OUT R24 www.ti.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) (2) VALUE UNIT VCC+ Supply voltage 22 V VCC– Supply voltage –22 V VID Differential input voltage (3) ±44 V VI Input voltage range (any input) VCC+ to (VCC– – 0.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC = 5 V, at specified free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V αVIO Temperature coefficient of input offset voltage VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V IIO Input offset current VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V IIB Input bias current VO = 2.5 V, RS = 50 Ω, VIC = 2.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com OPERATING CHARACTERISTICS VCC = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT SR+ Positive slew rate AVD = –1, RL = 2 kΩ , CL = 500 pF 45 V/μs SR– Negative slew rate AVD = –1, RL = 2 kΩ (1), CL = 500 pF 42 V/μs To 0.1% 0.16 To 0.01% 0.22 ts Settling time AVD = –1, 2.5-V step Vn Equivalent input noise voltage RS = 20 Ω Vn(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 1 Hz 0.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC = ±15 V, at specified free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VIC = 0, RS = 50 Ω αVIO Temperature coefficient of input offset voltage VIC = 0, RS = 50 Ω IIO Input offset current VIC = 0, RS = 50 Ω IIB Input bias current VIC = 0, RS = 50 Ω VICR Common-mode input voltage range TA (1) MIN 25°C 200 Full range 25°C 7 –0.7 25°C –15 to –15.3 to 13 13.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com OPERATING CHARACTERISTICS VCC = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR+ Positive slew rate AVD = –1, RL = 2 kΩ, CL = 100 pF 27 45 V/μs SR– Negative slew rate AVD = –1, RL = 2 kΩ, CL = 100 pF 27 42 V/μs To 0.1% 0.34 To 0.01% 0.4 ts Settling time AVD = –1, 10-V step Vn Equivalent input noise voltage RS = 20 Ω Vn(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 1 Hz 0.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Table 1.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE TLE2141 DISTRIBUTION OF INPUT OFFSET VOLTAGE 20 24 18 IIIO IO − Input Offset Current − nA Percentage of Units − % 20 236 Units Tested From 1 Wafer Lot VCC ± = ± 15 V TA = 25°C P Package 16 12 8 4 VO = 0 VIC = 0 16 14 12 10 VCC ± = ± 2.5 V 8 6 VCC ± = ± 15 V 4 2 0 −75 −50 −25 0 25 50 75 100 125 150 TA − Free-Air Temperature − °C 0 −800 400 0 −400 VIO − Input Offset Voltage − µV 800 Figure 2.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE 15 RL = 2 kΩ TA = 25°C 18 VCC ± = ± 15 V V OM − Maximum Peak Output Voltage − V V OM − Maximum Peak Output Voltage − V 24 12 VOM + 6 0 −6 VOM − −12 −18 3 6 9 12 15 18 21 RL = ∞ 14.2 VOM + 13.8 RL = 2 kΩ −13.8 −14.2 RL = 2 kΩ VOM − −14.6 RL = ∞ −15 −75 −50 −25 0 25 50 75 100 125 150 TA − Free-Air Temperature − °C − 24 0 14.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com MAXIMUM PEAK OUTPUT VOLTAGE vs SETTLING TIME AVD = −1 VCC ± = ± 15 V TA = 25°C 10 7.5 0.1% 0.01% 5 2.5 Rising 0 Falling −2.5 0.01% −5 0.1% −7.5 −10 −12.5 0 100 200 300 400 500 V O(PP) − Maximum Peak-to-Peak Output Voltage − V VVOM OM − Maximum Peak Output Voltage − V 12.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE COMMON-MODE REJECTION RATIO vs FREQUENCY 120 VCC ± = ± 15 V TA = 25°C CMRR − Common-Mode Rejection Ratio − dB CMRR − Common-Mode Rejection Ratio − dB 140 120 100 80 60 40 20 0 100 1k 100 k 10 k f − Frequency − Hz VIC = VICRmin VCC = 5 V 116 112 108 VCC ± = ± 15 V 104 100 −75 −50 −25 0 25 50 75 100 125 150 TA − Free-Air Temperature − °C 1M Figure 18. Figure 19.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 4 3.8 VO = 0 No Load TA = 125°C IIDD CC − Supply Current − mA IIDD CC − Supply Current − mA 3.6 3.5 TA = 25°C 3 TA = − 55°C 2.5 VCC ± = ± 15 V 3.4 VCC ± = ± 2.5 V 3.2 3 VO = 0 No Load 2.8 −75 −50 −25 0 25 50 75 100 125 150 TA − Free-Air Temperature − °C 2 0 4 8 12 16 20 |VCC ±| − Supply Voltage − V 24 Figure 22. Figure 23.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com NOISE CURRENT vs FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 6 TA = − 55°C 4 TA = 25°C 2 TA = 125°C 0 1 10 100 1k 10 k f − Frequency − Hz THD + N − Total Harmonic Distortion + Noise − % In − Noise Current − pA/ Hz 8 1% VO(PP) = 20 V VCC ± = ± 15 V TA = 25°C 0.1% AV = 10 RL = 600 Ω AV = 10 RL = 2 kΩ 0.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com PHASE MARGIN vs LOAD CAPACITANCE GAIN MARGIN vs LOAD CAPACITANCE 14 12 TA = − 55°C 8 6 TA = 125°C 50° TA = 125°C 40° 30° 10° 2 TA = 25°C 100 1000 CL − Load Capacitance − pF Figure 34.
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TLE2141-Q1 SLOS525 – SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Input Offset Voltage Nulling The TLE2141-Q1 offers external null pins that can be used to further reduce the input offset voltage. If this feature is desired, connect the circuit of Figure 36 as shown. If external nulling is not needed, the null pins may be left unconnected. IN+ IN- 3 2 + 6 OUT – 5 5 kW 1 OFFSET N2 OFFSET N1 1 kW VCC– (split supply) GND (single supply) Figure 36.
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PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2011 PACKAGING INFORMATION Orderable Device TLE2141QDRQ1 Status (1) ACTIVE Package Type Package Drawing SOIC D Pins Package Qty 8 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.