Datasheet

+
-
OUT
IN+
IN-
OFFSET N1
OFFSET N2
TLE2141-EP
TLE2142-EP
TLE2144-EP
SLOS577 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
The devices are stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz
at this high loading level. As such, the TLE214x are useful for low-droop sample-and-holds and direct buffering of
long cables, including 4-mA to 20-mA current loops.
The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as
is evidenced by a 900- µ V maximum offset voltage and 1.7- µ V/ ° C typical drift. Minimum common-mode rejection
ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.
Device performance is relatively independent of supply voltage over the ± 2-V to ± 22-V range. Inputs can operate
between V
CC –
– 0.3 V to V
CC+
– 1.8 V without inducing phase reversal, although excessive input current may flow
out of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearly
rail-to-rail output swing of V
CC –
– 0.1 V to V
CC+
– 1 V under light current-loading conditions. The device can
sustain shorts to either supply since output current is internally limited, but care must be taken to ensure that
maximum package power dissipation is not exceeded.
Both versions can also be used as comparators. Differential inputs of V
CC ±
can be maintained without damage to
the device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good indication
as to output stage saturation recovery when the device is driven beyond the limits of recommended output swing.
The TLE214x devices are available in industry-standard 8-pin and 16-pin small-outline packages. The devices
are characterized for operation from – 55 ° C to 125 ° C.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Single SOIC – D (8 pin) Reel of 2500 TLE2141MDREP 2141EP
– 55 ° C to 125 ° C Dual SOIC – D (8 pin) Reel of 2500 TLE2142MDREP
(3)
TBD
Quad SOIC – DW (16 pin) Reel of 2000 TLE2144MDWREP
(3)
TBD
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com .
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
(3) Product Preview. Contact your TI sales representative for availability.
SYMBOL
A. OFFSET N1 and OFFSET N2 are available only on the TLE2141.
2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLE2141-EP TLE2142-EP TLE2144-EP